完整後設資料紀錄
DC 欄位語言
dc.contributor.author張文明en_US
dc.contributor.authorChang Win-Mingen_US
dc.contributor.author周復芳en_US
dc.contributor.authorChristina F. Jouen_US
dc.date.accessioned2014-12-12T02:53:16Z-
dc.date.available2014-12-12T02:53:16Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009313600en_US
dc.identifier.urihttp://hdl.handle.net/11536/78412-
dc.description.abstract本論文討論應用於射頻接收機的高頻電路設計且主要分為兩個主題探討。其中第ㄧ部份是增益可調切換式雙頻帶低雜訊放大器及一個新型切換轉導式偶次諧波降頻混頻器的分析和設計。另ㄧ部份是ㄧ個Ka頻帶的低雜訊放大器驗證,最後我們以一個K頻帶頻率信號源作為未來的研究專題。 緊接著我們設計並製作ㄧ個使用0.18um CMOS製程,操作在2.45GHz/ 5.25GHz的增益調整式雙頻帶低雜訊放大器。在高增益模式時,此放大器在2.45-GHz表現14.4dB的功率增益及3.54dB 的雜訊指數。在5.25-GHz則有12.02dB的功率增益及2.88dB的雜訊指數。此低雜訊放大器在雙頻帶皆有大約11dB的增益可調範圍, 我們使用0.18um CMOS製程設計並驗證切換轉導技術的新型偶次諧波降頻混器。此全整合的次諧波混頻器量測結果顯示使用4dBm的本地震盪器,在中頻10MHz可得到12.8dB的降頻轉換功率增益,-1.8dBm 三階諧波交會點,和 14.0dB DSB雜訊指數。 接下來,ㄧ個使用標準0.18um CMOS製程的三級Ka頻帶低雜訊放大器被製作及驗證。在32-GHz時,量測出12.08dB的功率增益及5.325dB的雜訊指數,總功率消耗為15.58毫瓦。 最後,一個使用0.18um CMOS 低相位雜訊X頻帶四項位壓控震盪器倍頻而成的K頻帶頻率訊號源已被模擬,此K頻訊號源也當作此論文的將來專題研究zh_TW
dc.description.abstractThis thesis discusses high frequency circuit design for RF receivers and it mainly includes two parts. One is the analysis and design of a switched dual-band LNA with variable gain and a new switched Gm sub-harmonic mixer. The other is the demonstration of a Ka band LNA, and finally a K band frequency source with X band low phase noise quadrature VCO is simulated for feature work. A switched dual-band low noise amplifier with four gain control modes operating at 2.45-GHz/5.2-GHz has been designed and demonstrated based on a 0.18-um CMOS process. In the high gain mode, the LNA approaches 14.4 dB maximum power gain and 3.54 dB DSB noise figure at 2.45-GHz. In the 5.25-GHz band, the maximum power gain is 12.02 dB and the DSB noise figure is 2.88 dB. A new prototype of sub-harmonic mixer using switched Gm technique is designed and implemented in a standard 0.18um CMOS technology. This fully integrated sub-harmonic mixer achieves measured high conversion power gain of 12.8 dB, -1.8 dBm IIP3, and 14.0 dB noise figure at 10-MHz with 4 dBm LO power. A 3-stage Ka band LNA has been designed and verified by using standard CMOS 0.18um process. The measured power gain at 32-GHz is 12.08 dB with noise figure of 5.325 dB while consuming 15.58 mW. Finally, a K band frequency source with X band 0.18um CMOS low phase noise quadrature VCO has been simulated. This K band frequency source is treated as feature work in our thesis.en_US
dc.language.isoen_USen_US
dc.subject雙頻帶zh_TW
dc.subject低雜訊放大器zh_TW
dc.subject偶次諧波zh_TW
dc.subject降頻混頻器zh_TW
dc.subjectKa頻zh_TW
dc.subjectK頻zh_TW
dc.subject壓控震盪器zh_TW
dc.subjectdual-bnaden_US
dc.subjectlow noise amplifieren_US
dc.subjectsub-harmonicen_US
dc.subjectdown convert mixeren_US
dc.subjectKa banden_US
dc.subjectK banden_US
dc.subjectvoltage-controlled oscillatoren_US
dc.title應用於IEEE 802.11a/b/g之雙頻帶低雜訊放大器和偶次諧波降頻混頻器以及使用0.18um CMOS製作之Ka頻低雜訊放大器和K頻壓控震盪器zh_TW
dc.titleA Dual-Band LNA and a Sub-harmonic Mixer for IEEE 802.11a/b/g Application and a Ka Band Low Noise Amplifier and a K Band VCO by Using 0.18um CMOS Processen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
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