低功率三階連續時間三角積分調變器之設計與製作

Abstract

隨著手持式電子產品的蓬勃發展(例如：筆記型電腦、手機、MP3播放器…等)，系統單晶片(SOC)在減少這些電子裝置的耗電和重量上，是一個很重要的關鍵。在可攜式的產品中，電池的重量以及大小常是造成產品重量及大小的關鍵，因此減低功率的消耗可以有效的減少電池的個數以及電池的壽命。此外，因為電晶體的密度會隨著製程的進步而提昇，如此會使降低功率消耗的技術顯的更 加重要。而在這類的電子產品上，軟體與硬體大多都是用數位的方法去實現，因此，一個高解析度、低功率耗電且面積小的類比數位轉換器是很重要的，因為如果橋接類比與數位兩種不同訊號的類比數位轉換器做得不夠好，會影響接下來許多數位電路效能。而三角積分類比數位轉換器就非常符合這個需求，因為它在有限頻寬的限制下可以達到非常高的解析度。除此之外，類比所佔的成份也相對比較少且對製程漂移的影響也比較小。因此，近幾年來三角積分類比數位轉換器都扮演著非常重要的角色。

三角積分類比數位轉換器在不同的應用範圍下通常會有兩種種類，一種是離散時間三角積分類比數位轉換器(Discrete-Time Sigma-Delta ADC)，因為它通常都是用交換電容的電路下實現，所以又稱為交換電容三角積分類比數位轉換器(Switched-Capacitor Sigma-Delta ADC)。一般而言，離散時間三角積分器為了在一個clock的時間可以快速的充放電到前級交換電容電路所儲存的電荷，所以它的積分器也就是OPAMP的規格，不管是頻寬、Slew Rate和Settling Time都要訂得比較高才行，然而對於連續時間而言，它不需要在一個clock的時間下做處理，所以它的積分器的規格可以訂的比較寬鬆一點，因此它的功率消耗會減少很多。

因此，為了將連續時間三角積分類比數位轉換器的優點應用在基頻的範圍內，我的研究主題就是做出一個適用於基頻範圍的超低功率消耗的連續時間三角積分類比數位轉換器，所消耗的功率與面積將會比用離散時間方式做出來的還要更低，以符合可攜式電子產品需要低消耗功率的趨勢。晶片是以台積電0.18微米標準互補式金氧半導體製程所製造。

Along with rapid growth of battery-powered portable devices, such as laptop, cellular phones, and MP3 player, system on a chip (SOC) is an important issue to help devices become smaller and lighter. Moreover, batteries almost dominate portable devices’ sizes and weight. Therefore, reducing the power dissipation in chip is desirable so as reduce the number of battery cells and extend the battery lifetime as much as possible. Furthermore, the raising complexity on a chip results in an increase of power density, which leads to even higher demand for power reduction techniques. In today’s device application, digital circuits dominate the whole chip function. However, analog-to-digital converter (ADC) is also indispensable. Under these conditions, sigma-delta (ΣΔ) ADCs are very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation.

Typically, there are two kinds of ΣΔ ADCs. The first one is discrete-time (DT) ΣΔ ADC and another is continuous-time (CT) ΣΔ ADC. The DT ΣΔ ADC also called the switched-capacitor (SC) ΣΔ ADC because of using switched capacitors. Generally, in order to charge and discharge the capacitors in one clock time, the specification of an OPAMP , such as gain-bandwidth, slew rate and settling time, will be increased. But for CT ΣΔ ADC, it doesn’t need to process signals within a clock time, so the requirement of integrator will be reduced. This results in further power decreasing. In order to combine the advantages of the CT ΣΔ ADC system with low-frequency low-power applications, this research focuses on ultra low power audio CT ΣΔ ADC. The power consumption and area will be reduced compared with DT ΣΔ ADC. The chip has been fabricated by TSMC 0.18-um CMOS process.