應用於藍芽接收機降頻電路之研究

Abstract

本論文旨在利用金氧半製程實現符合藍芽接收機規格的低中頻降頻電路，此電路包含本地振盪源、低雜訊放大器與混波器，接收頻率範圍2.4GHz~2.4835GHz，其中頻為2MHz。本地振盪源採用正交電感電容振盪器，以對稱疊接方式降低功率損耗與相位雜訊、提供2.1GHz~2.8GHz的頻寬與1.36V的輸出電壓振幅，其正交相位誤差小於1°。為了完整探討本地振盪源，本論文亦研究以環路振盪器為核心的鎖相迴路，其中新型兩級環路振盪器利用交錯耦合架構使單級滿足90°相位移，並達到1.5V的輸出電壓振幅、0.49GHz~2.6GHz頻率範圍量測值及4mW的功率消耗，整體電流消耗量測為10mA。 低雜訊放大器採用疊接式電感退化型架構改善雜訊指數與IIP3，其雜訊指數為2dB、IIP3為-4.2dBm；混波器採用單平衡架構節省功率消耗，並以PMOS為開關以降低雜訊指數，其雜訊指數為12.4dB，IIP3為7.1dBm。此降頻電路設計採用TSMC 0.18um製程，其電壓增益約18dB、雜訊指數為10dB、IIP3為-12dBm，整體電流消耗為15mA。

The purpose of this paper is to implement a CMOS Low-IF Down-Conversion circuit for Bluetooth Receiver. The circuit consists of LO, LNA, and mixer. The RF signals from 2.4GHz to 2.4835GHz are down-converted to a 2 MHz low IF. The LO is realized by the quadrature LC-tank cross-coupled VCO to achieve low power consumption, good phase noise, and large tuning range. The output amplitude achieve 1.36V with phase mismatch between I and Q signal less than 1°. For comparison, the two-stages ring VCO is also examined. The output amplitude and power consumption are 1.5V and 4mW, respectively. The measured frequency range is from 0.49GHz to 2.6GHz. As regards to the receiver, a low noise amplifier with high linearity is obtained by using the cascade inductive degeneration LNA. The NF achieves 2 dB with IIP3 equals to -4.2 dBm. The mixer is realized by single-balance structure with PMOS as its switches, the NF achieves NF 12.4 dB and IIP3 7.1 dBm. This down-converter is manufactured by TSMC 0.18um process. The conversion gain is 18 dB, NF 10 dB, and IIP3 -12 dBm. The total current consumption is 15mA.