低功率時脈網路取向多階層化電路擺置

Abstract

製程進步的演化迅速，特別在進入深次微米製程後，時脈網路在許多高速的電路設計上消耗了超過40%的總功率。而現今產品廣泛地需要可攜式功能，如何將晶片的功率消耗做有效的規劃，是一個重要的課題。 我們提出了一個低功率電路時脈取向網路結構，在以各個元件的活動率為基礎下進行。我們主要採用的方法為閘控時脈網路加上使用非零時脈歪斜的時脈最佳化理論來使電路的時脈網路縮減，並且是以電路活動的機率做最佳化的考量基礎，使電路在考慮原來的時脈限制下，對功率消耗做最佳化。並且在進行電路佈局時，可將暫存器利用絕對線長法移到我們所考慮的最佳化位置，且採用的方法為多階層化電路佈局，以加快速度，在每一層都先根據該階層的狀況，進行電路佈局並且使用絕對線長設定一個暫存器的錨釘來限制其符合我們所建構最佳時脈網路，且同時考慮系統面積與系統總線長。使用一個有系統的方法減少功率的消耗。

As the process technology entering the deep sub-micron design era, the power consumption of clock networks dominates over 40% of the total power in modern high performance VLSI designs. Particularly, the power design is substantial in portable electronic devices. How to optimize the power consumption of chips is an important issue. The purpose of this thesis is to construct a low power clock network in the placement level. We use the gated clock method and non-zero clock skew optimization to reduce the total switching capacitance of clock networks. It is based on circuit block activity to minimize the clock network power under clock period constraint and it is implemented on a multilevel placer for the reason of processing complex circuits. During each level of the hierarchical placement, it uses anchors determined by the Manhatern circle to constrain the flip-flop in the desired region and it constructs an optimal clock network considering the total area and wire length. The experimental results show that our methods indeed reduce the clock network power consumption.