一個針對維特比解碼器設計之全客戶式殘存記憶單元與低功率脈衝邊緣觸發閂鎖暫存器

Abstract

維特比解碼器被認為在提供優異性能的同時，維持了合理的編碼複雜度與適當的運算資源而被廣泛地使用在現今的通訊系統錯誤更正機制中卷積碼的處理；然而由於電池壽命有限，低功率訴求在現今通訊領域的超大型積體電路設計之中成為了比過往更重要的議題，因此在本論文，我們針對維特比解碼器設計一個由大量暫存器組成，基於暫存器交換架構之帶有低功率特徵的全客戶式殘存記憶單元。首先本論文提出一個新的暫存器架構：低功率低擺幅靜態邊緣觸發閂鎖暫存器；由於該暫存器具有較低之時脈節點電容及較少電晶體數目兩樣特徵，在功率以及面積方面的考量都非常設合於本殘存記憶單元的設計。此外除了零點一三微米互補式金氧半導體製程下的模擬，我們特別於九十奈米製程的模擬中觀察了漏電流功率的現象。藉由全客戶式設計流程的輔助，本論文完成了全客戶式殘存記憶單元的實體電路佈局實作，且在特定的測試樣本之下，所消耗的功率僅是電路輔助設計軟體所合成之殘存記憶單元的百分之二十七點三。本論文電路佈局實作的環境是台積電零點一三微米互補式金氧半導體製程。

Viterbi decoders are widely used in communication systems as decoding convolutional codes which provide a superior error correction capacity while maintaining a reasonable coding complexity and computing resource. However, power dissipation has become a critical issue in modern communication systems which have emphasized low power features due to shortage of battery life. In this thesis, a fully custom register-exchange based SMU hard macro which is composed of a lot number of low power registers is presented for Viterbi decoders. We first propose our low power low swing static edge-triggered latch (ETL) which is very suitable for the register-exchange SMU design due to its less clock loading and fewer transistors number at power and area domain. We not only simulate proposed low swing static ETL in 0.13 um CMOS process, but also in 90 nm CMOS process especially interesting in leakage power dissipation. Then we based on the proposed static ETL to construct our low power SMU hard macro by means of the fully custom design flow, and the power consumption under the specified test pattern is merely about 27.3% as compared with the synthesized SMU from EDA synthesizer. The Layout implementation environment of this work is in TSMC 0.13 um CMOS process.