Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 許豐庭 | en_US |
dc.contributor.author | Feng-Ting Xu | en_US |
dc.contributor.author | 林振德 | en_US |
dc.contributor.author | Jenn-Der Lin | en_US |
dc.date.accessioned | 2014-12-12T02:53:58Z | - |
dc.date.available | 2014-12-12T02:53:58Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009314563 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/78538 | - |
dc.description.abstract | 本文針對Ⅲ-Ⅴ族高頻覆晶構裝,分別利用有限元素與有限體積等數值模擬方法,研究構裝體於接合製程後之殘留應力以及晶片工作後最終熱應力分析。對於負責傳輸訊號且容易受破壞的凸塊及金線,本文考量雙線性之塑彈性材料以增加模擬可信度;此外以不增加構裝體模型整體尺寸為原則,藉由改變金線厚度、凸塊材料、凸塊半徑與高度以及基板材質等變數,我們探討金線與凸塊部分的應力及變形行為。 研究結果顯示,金線厚度增加雖有益於構裝體的散熱效果,但也會提高凸塊與金線的熱應力值。對於凸塊材質的選擇上,由於機械與熱傳性質上的差異,銅凸塊比金凸塊更可以有效降低其本身的殘留應力與晶片工作後的最終熱應力。至於基板材料AlN與Al2O3二者之相比較結果,AlN基板不但可以有效降低晶片溫度,且金線部分的熱應力值也較採用Al2O3基板時要低,此外金線與凸塊部分亦將不會產生較大之位移變化量,亦即可避免翹曲現象發生。 | zh_TW |
dc.description.abstract | Considering the Ⅲ-Ⅴ group high frequency flip chip package, in this thesis we apply finite element and finite volume methods to investigate the residual stress after bonding process and total thermal stress when chip is at work. For the purpose of improving the reliable result of simulation, it’s necessary to include the bilinear plastic feature of the material into wire and bump, which take charge of signal transmission. In this study, we analyze the thermomechanical phenomenon in wire and bump at fixed dimensions, and various values of wire thickness, bump radius and height, for two kind materials of substrate. The results show that thickened wire will benefit on the thermal dissipation in package, but it also makes the thermal stress of wire and bump rise up. Because the thermal and mechanical properties in Cu bump are different from those in Au bump, is found that using Cu bump can decrease the residual and final stresses much more efficiently than Au bump. Comparing with the cases of Al2O3 substrates, results show that AlN substrates can not only significantly reduce the maximum temperature in chip, but also lower the stress in wire. Besides, it can avoid deflection in wire and bump. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 覆晶構裝 | zh_TW |
dc.subject | 熱應力 | zh_TW |
dc.subject | 殘留應力 | zh_TW |
dc.subject | Flip-Chip Package | en_US |
dc.subject | Thermal Stress | en_US |
dc.subject | Residual Stress | en_US |
dc.title | 高頻覆晶構裝之熱應力分析 | zh_TW |
dc.title | An Analysis for Thermal Stress of High Frequency Flip-Chip Package | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 機械工程學系 | zh_TW |
Appears in Collections: | Thesis |
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