考量管線時間之延伸指令集

Abstract

延伸指令集(ISE)是一種有效的方式可以滿足在許多應用上不斷增加的電路以及速度的需求。ISE產生的流程通常包含了ISE Exploration以及ISE Selection兩個步驟，在ISE Exploration的步驟中，為了要達到最高的加速效果，大多數的研究都直接使用速度最快的實做方式來實做每一個在特殊的功能單元(ASFU)中的基本運算，而ASFU也就是複雜執行延伸指令集的功能單元，儘管如此，最快速的實作方式卻不一定是最好的選擇，在選擇ASFU中的運算的實作方式時，有兩點重要的考量：(1)ASFU的執行時間必須符合管線時間的限制，也就是必須與原本管線時脈的整數倍相同，並且在(1)的前提下，(2)ASFU必須使用最少的額外面積，為了要滿足這些考量，我們提出了一個ISE Exploration的演算法不只可以探索ISE候選者，也同時考慮了它們的實作方式以期能夠減少最多的執行時間，並且在此同時使用較少的面積。使用Mibench的模擬結果顯示，與沒有考量管線時間的ASFU比較，這個方法可以額外節省35.28%、15.92%以及22.41%(最大、最小以及平均)的面積，而且最多只有1.06%的效能損失，模擬的結果更進一步的顯示我們的方法在足夠小的例子中，找出來的結果與最佳解相當接近，但卻節省了相當多的計算時間。

Instruction set extension (ISE) is an effective way to meet the growing efficiency demands for both circuit and speed in many applications. ISE generation flow usually consists of ISE exploration and ISE selection phases. In ISE exploration, in order to achieve the highest speed-up ratio, most works deploy the fastest implementation option for each operation in application specific functional unit (ASFU) which executes instruction in ISEs. Nevertheless, the fastest implementation option may be not the best choice. Two considerations are important in selecting an implementation option for each operation in ASFU: (1) the execution time of an ASFU should meet pipestage timing constraint, i.e. fit to an integral number of original pipeline cycles; and (2) under (1), the ASFU should use the least silicon area. To conform to these considerations, we propose an ISE exploration algorithm which not only explores ISE candidates but also their implementation options to minimize the execution time meanwhile use less silicon area. Results with MiBench indicate that the approach achieves up to 35.28%, 15.92% and 22.41% (max., min. and avg.) of further reduction in extra silicon area usage and only has maximally 1.06% performance loss compared with the approach without the consideration of pipestage timing constraint for ASFU. Furthermore, simulation results also show that our approach is very close to optimal one, but takes much less computing time.