可被窄寬度運算共用之單一管線資料路徑設計

Abstract

現今大多數之處理器之架構都採32位元或者更高之位元數. 然而整數運算大多數時間都不會用到資料路徑中完整的寬度. 若將Source Operand Bus及ALU分割為多組block, 則此資料路徑便具備同時處理一道以上運算之能力.本論文提出讓單一資料路徑被兩道具備窄寬度特性之指令合用之設計. 讓其中一道運算之Operand Block以反轉(Turnaround)之次序, 來達到極有效率之資料路徑合用機制.相較於傳統以直接Shift方式, 本設計不論就面積與電路延遲上, 都有較佳之表現. 此外, 本論文亦提出一縮短ALU因分割為多組ALU Block所造成延遲之設計. 最後, 本論文提出將此機制整合至一典型五階MIPS管線之方式.

Most general-purpose processors and embedded processors have 32-bit word widths or wider. However, integer operations rarely need the full 32-bit dynamic range of the datapath. If we partition the operand bus, result bus, and ALU into several blocks, the datapath could perform more than one operation in parallel. In this thesis, mechanisms to join two narrow-operand operations together to share a single datapath are proposed. We proposed one novel ALU-sharing scheme by turning around operation-block ordering. Efficient designs to merge operands to share buses and ALU based on the technique are proposed and discussed. Compared with traditional “shift” approach, the turnaround approach has many advantages on area and delay. Besides, a technique to mitigate the delay overhead of the partitioned ALU by swapping operands is proposed. We also made performance simulation to help decide how to partition the datapath. Finally, how to integrate such datapath into a MIPS five-stage pipeline and required modifications are discussed.