n型通道與p型通道完全鎳自我對準矽化源/汲與閘極複晶矽薄膜電晶體之研究

Abstract

在先進互補式金氧半導體元件裡，當接觸尺寸縮小至奈米等級，源極及汲極的接觸電阻也會隨之增加。因此，金屬矽化物的技術應用在源極及汲極已經被開發用來同時降低接觸電阻及接面寄生電阻。所以，具有與矽基材完好介面特性的金屬矽化物是元件製程的重要考量。相同的問題也會發生在多晶矽薄膜電晶體上，超薄的多晶矽薄膜電晶體限制了元件的驅動電流。然而，為了減少多晶矽薄膜電晶體的寄生電阻，在很多研究裡採用了完全鎳自我對準矽化反應去解決這個問題。 近幾年來，完全矽化鎳閘極被廣泛地研究來取代金屬閘極，金屬矽化鎳閘極具有低電阻率、消除多晶矽閘極空乏現象、可調變的功函數以及整合容易等優點。同樣地，完全矽化鎳源/汲極也被廣泛地應用來減少接觸電阻以及接面寄生阻值。此外，就電阻而言，矽化鎳(NiSi)的片電阻是跟二矽化鈦(TiSi2)和二矽化鈷(CoSi2)差不多的。然而，鎳金屬矽化物沒有窄線寬效應(narrow line effect)，且鎳金屬矽化物可以在低溫(400~600℃)時形成而不會有結塊效應(agglomeration effect)。還有在矽化鎳的形成過程當中，它消耗較少的矽，所以它可以形成較淺的接面。這些都是鎳金屬材料所具有的優點。 在本論文研究中，N型和P型的完全鎳自我對準矽化源/汲與閘極多晶矽薄膜電晶體(FSA-TFTs)已經被成功地製造出來。另外，為了和完全鎳自我對準矽化源/汲與閘極多晶矽薄膜電晶體比較，我們也特地製造了局部鎳自我對準矽化源/汲與閘極多晶矽薄膜電晶體(partially salicided TFTs)。特別地，在此研究裡我們也去比較了金屬快速熱製程溫度與時間對元件特性的影響。由完全鎳自我對準矽化多晶矽薄膜電晶體和局部鎳自我對準矽化多晶矽薄膜電晶體以及傳統的多晶矽薄膜電晶體比較，完全鎳自我對準矽化多晶矽薄膜電晶體有較好的特性。其原因為有較小的源/汲極與閘極片電阻以及減少的寄生阻值，且能夠有效的鈍化矽基材裡的缺陷。而且,它可以有效地抑制浮接基體效應(floating-body effect)和寄生雙極性接面電晶體效應(parasitic bipolar junction transistor action)。因此，我們從實驗結果發現，完全鎳自我對準矽化多晶矽薄膜電晶體能夠得到較高的驅動電流、較低的漏電流、較好的次臨界特性、較少的臨界電壓變化量和較大的場效遷移率等。所以，完全鎳自我對準矽化多晶矽薄膜電晶體的特性適合用在需要穩定的臨界電壓和大的崩潰電壓。

In CMOS devices, as the dimension of devices scaling down, the short channel effects are more severe. Similar problem also happens in the poly-Si TFT. Large parasitic resistance results in the limitation of the ON current in the thin-channel poly-Si TFTs. In order to decrease the parasitic resistance of the poly-Si TFTs and control threshold voltage, it is needed to use heavy channel doping. However, the carrier mobility will be reduced and device performance will be degraded, too. For this reason, the single metal gate with suitable work function will be used to control the threshold voltage in the future. However, metal gate let integration be difficult with the self-aligned process. Recently, the full silicide (FUSI) NiSi is investigated as an alternative metal-gate. The fully Ni-salicided gate structure has several advantages, such as low resistivity, elimination of poly depletion effect, tunable work function, and better process compatibility. Moreover, Ni-salicided S/D structure can drastically decrease the parasitic resistance and passivate the defects of S/D junction. In addition, the sheet resistivity of NiSi is comparable with that of TiSi2 and CoSi2, and NiSi does not have narrow line effect, and NiSi can be accomplished at low temperature (400~600℃) without agglomeration effect. During the formation of NiSi, it is the less silicon consumption. So it can form shallower junction. In this thesis, n-channel and p-channel poly-Si thin-film transistors (FSA-TFTs) with fully Ni self-aligned silicided (fully Ni-salicided) source/drain and gate structure have been successfully fabricated. In addition, we also fabricate partially Ni-salicided S/D and gate in order to compare with FSA-TFTs. Specially, we also investigated the influence of RTA temperature and time in this study. The FSA-TFTs exhibit the best electrical characteristics because of FSA-TFTs have small S/D and gate sheet resistance and low parasitic resistance. Moreover, FSA-TFTs can effectively suppress the floating-body effect and parasitic bipolar junction transistor action compared with conventional TFTs. Experimental results show that the FSA-TFTs give higher on-state current, lower off-state leakage current, improved subthreshold characteristics, less threshold voltage variation, and larger field-effect mobility compared with control TFTs. The characteristics of the FSA-TFTs are suitable for high performance driving TFTs with a stable threshold voltage and large breakdown voltage.