具高精確度11位元一階連續時間Σ-Δ類比至數位轉換器

Abstract

本論文中,將設計與分析一個十一位元, 46.08MHz的取樣頻率, OSR= 256,高精確度度一階連續時間互補式金屬氧化物半導體Σ-Δ類比/數位轉換器.為了同時達到較好的效能和高速調變的目的,本設計採用了全差動式的電路架構並運用一個消耗2.6 mW,高速的,兩級架構的運算放大器和高速比較器以及具有1/4時脈的歸零數位/類比轉換器形成回授路徑的技巧來完成此設計. 經過調變後,為了同時達到平均和降頻的目的,數位平均降頻的濾波器是不可或缺的,關於這部分是利用MATLAB套裝軟體中的SIMULINK 來實現. 此轉換器使用台積電0.25μm 1P5M n-well互補式金氧半的製程製造.整個晶片佈局的面積是915 x 932 μm2.輸入電壓範圍為1V, 2.5V的操作電壓.量測的結果在44KHz的輸入訊號且取樣頻率在46.08MHz的情況下,信號對雜訊及諧波比值(SNDR)為66dB (10.67 bits)以及信號對雜訊(SNR) 比值為66.2dB (10.7 bits).

In this thesis, a 11-bit 46.08MHz sampling rate, OSR=256, high- precision first–order continuous-time CMOS sigma-delta analog-to-digital converter (ADC) is designed and analysis. In order to get better performance and high-speed modulation, using fully differential circuit architecture, including the high-speed two-stage opamp which dissipate 2.6mW, high-speed comparator and the feedback loop with 1/4 clock return-to-zero (RTZ) digital-to-analog converter (DAC) is implemented. After the modulation, the digital decimation filter is needed to average filter function and rate reduction function simultaneously. The SIMULINK of the MATLAB implements the part of the digital decimation filter. The ADC is fabricated with TSMC 0.25um 1P5M n-well CMOS technology. The total layout area is 915 x 932 μm2. Input voltage range of the ADC is 1V with 2.5 V supply voltage. Measured performance includes 66dB (10.67 bits) of SNDR (Signal-to-Noise-plus-Distortion-Ratio) and 66.2dB (10.7 bits) of SNR (Signal-to-Noise-Ratio) for 44KHz input at 46.08MHz sampling rate.