在閉迴路上使用資料相位校正器之10-Gb/s CMOS時脈與資料回復電路

Abstract

本篇論文提出一個適用於晶片上多通道之資料校正(data-deskew)時脈與資料回復(CDR)電路。 此CDR系統是藉由調整數位控制延遲線(DCDL)內的資料延遲量來回復單通道10-Gb/s之突發資料封包。在最佳選取點獲取之後，資料週期的中點會對準時脈的選取邊緣，同時由通道所造成的偏移也獲得補償。 此CDR是一階系統，因此本質上就是穩定的。在傳送和接收端最大時脈抖動差量合於規範的前提下，它可以鎖定的頻率誤差為1000 ppm。又，閉迴路的特性使得此系統內之抖動為一低通模式。 所有的電路方塊均採用數位電路的實現方式。透過可信度計數器內部所採用之多數決(majority-vote)方式來達到快速鎖定（平均為110個位元時間）。在此系統中存在兩個關鍵設計：1)是高速、大擺幅之CMOS延遲線設計，2)是滿足迴路延遲之設計條件。 此外，這篇論文使用TSMC 0.13-μm CMOS製程，實現了一個10-Gb/s的數位傳接器。

This thesis proposes a data-deskew clock and data recovery (CDR) architecture for the on-chip multi-channel timing recovery. This CDR recovers the 10-Gb/s/ch burst data packet by adjusting the data delay in the digitally controlled delay line (DCDL). After the acquisition of the optimal sampling phase, the midpoint of data period aligns to the sampling clock. The data skew between channels is also compensated. This CDR is first-order and therefore inherently stable. It can track the specified 1000-ppm frequency error as long as the peak-to-peak clock jitter between the transmitter and the receiver sites is confined to the specification. And, the closed loop characterizes the high-band-limited jitter in this system. All building blocks adopt digital circuits. Fast acquisition (110-bit time in typical case) is achieved by the majority-vote scheme in the confidence counter. Two critical designs exist in this digital-circuit CDR: 1) high-speed large-swing CMOS DCDL deign, and 2) meeting the loop-latency constraint. In addition, a digital implementation of the 10-Gb/s transceiver is realized in TSMC 0.13-μm CMOS technology.