應用於1.5伏特3~10-GHz超寬頻頻率合成器

Abstract

UWB(Ultra-Wideband；超寬頻) 是一種以低功率、高速傳輸資料的短距離無線通訊技術，利用ns至ps 的非正弦波窄脈冲傳輸。由於目前無線通訊系統的傳輸速率要求越來越高，例如: Bluetooth(藍芽)的傳輸率要 1MHz/bps， WLAN的Date Rate大約54MHz/bps。 但在一些產品像IEEE 1394 cables; 3G cell phones; print and external storage devices的Date Rate都在幾百Mbps，而UWB的Data Rate從55到480Mbps，其高Date Rate的產品應用範圍就可以很寬泛，再加上頻帶非常寬及傳輸功率非常小，以致於抗干擾能力很強。綜合以上特點，所以UWB的架構才會孕育而生。因此已有一些UWB Frequency Synthesizer成功的以CMOS製作。但除了此電路有完整的頻率範圍(3432MHz~10032MHz)及低功率消耗(55.1mW~161.62mW)之外，其餘的發表均僅止於一部份的頻率範圍及高低功率消耗。這主要是因為在頻寬超過6~7GHz後，將CMOS整合於收發機中仍有一定的困難度。本篇論文闡述一個應用於3~10 GHz之超寬頻頻率合成器的設計方法與製作技術並依據國際電子電機學會所制定的802.15.3a規格作設計。論文中提出一個新的架構是由一個負迴授的鎖相迴路為主體，它包含的元件有相位頻率偵測器(Phase Frequency Detector)、電荷充放器(Charge Pump)、迴路濾波器(Loop Filter)、壓控振盪器(Voltage Controlled Oscillator) 、VCO緩衝器(VCO Buffer)、多相位濾波器(Poly Phase Filter)、 單邊帶混波器(SSB Mixer)、電流模式邏輯除法器(CML Divider)、 頻帶選擇器(Band Selector)組合而成。便可得到整個頻率合成器所需要的頻段(3432MHz~10032MHz) ，並且整合於單一晶片中。 在晶片設計上，針對一個1.5V 3~10GHz的頻率合成器，以0.18μm 1P6M CMOS製程完成。在1.5V的操作電壓下，功率消耗為55.1~161.62 mW，晶片面積為1900μm×1900μm。

UWB (Ultra-Wideband; Ultra wide band) is a kind of wireless communication technology of short distance of transmitting the materials with low power, at a high speed; utilize ps or ns non- sinusoidal wave narrow pulse to Transmission. Because the transfer rate of the wireless communication system requires higher and higher at present, for example: data rate of Bluetooth require 1MHz/bps, date rate of WLAN probably 54MHz/bps. But look like IEEE 1394 cables in some products; 3G cell phones; date rate of print and external storage devices is in several hundred Mbps, and data rate of UWB is from 55 to 480Mbps, high products of Date Rate its range of application can very wide to suffused. In addition, frequency band very wide to transmit power very much little, anti-interference very capable. According to synthesize the above characteristic, so the structure of UWB will just be arisen. So already some UWB frequency synthesizer has been made successfully with CMOS process. But except this circuit has intact for frequency range (3432MHz~10032MHz) and low power consumption (55.1mW~161.62mW), the rest are issued and only stopped in the frequency range of a part and high power consumption. This because in frequently wide to after exceeding 6~7 GHz, is it still have sure difficulty in transceiver to combine CMOS mainly. This thesis is explained and according to 802.15.3 a which the international electronic electrical machinery society make in an ultra wide-band frequency synthesizer design method to apply 3~10 GHz and manufacturing technology. It is a subject by the phase lock loop circuit that negative feedback a new structure in the thesis, the frequency synthesizer is composed of a phase frequency detector, a charge pump, a loop filter, a VCO, a VCO buffer, four poly phase filter, three SSB mixer, five CML divider, two band selector be make up. Can receive the frequency band (10032MHz of 3432MHz) that the whole frequency synthesizer need, and combine in the single chip. On chip design, a 1.5V 3~10GHz frequency synthesizer, make with 0.18um 1P6M CMOS process finish. Under the voltage of operation of 1.5V, power consumption is 55.1~161.62mW, the area of the chip is 1900μm * 1900μm.