懸浮閘和SONOS非揮發性記憶體元件特性及可靠度分析之研究

Abstract

在本研究中，我們製作和描述n 型通道的懸浮閘與SONOS非揮發性快閃記憶體元件特性。這篇論文主要著重致力於懸浮閘和SONOS元件的操作特性分析，如寫入與抹除操作以及相關的可靠性之議題。 由於閘極到汲極之間的藕合效應問題，所以懸浮閘元件被觀察到有嚴重的短通道效應。所幸這是可以使用介於控制閘與元件通道之間薄的ONO層之SONOS 元件結構來緩和這個現象。在本篇論文中，我們也探討在熱應力下資料保存的影響與相關儲存電荷流失的路徑。再者我們觀察到SONOS元件ONO層頂端較薄的矽氧化層所引發的可靠性議題，其中又以影響最顯著的直接穿隧電荷流失效應為最。在另外一方面，隨著寫入/抹除的次數增加，懸浮閘元件會產生重要的電子的捕捉現象而導致縮小臨界電壓的操作範圍。此外我們觀察到兩種記憶體元件寫入方法所引發的界面缺陷現象，尤其是SONOS元件。雖然SONOS元件的通道初始二次電子(CHISEL)寫入方式會大量地增加界面狀態密度和導致次臨界電壓擺幅與跨導的退化，然而我們從結果可以看出既使在多次重覆寫入/抹寫狀態後，一個可以接受的臨界電壓操作範圍是得以維持。

In this work, we fabricated and characterized n-channel floating-gate (FG) and silicon-oxide-nitride-oxide-silicon (SONOS) flash non-volatile memory devices. Major focus is paid on operation characteristics like programming and erasing, as well as the associated reliability issue. Worse short-channel effect (SCE) is observed for the FG devices, owing to gate-to-drain coupling issues. This phenomenon could be relaxed using the SONOS structure, thanks to the thin ONO layer between the control gate and the channel. We also investigated the impact of thermal stress on the data retention and the related charge loss paths. Furthermore, significant direct tunneling (DT) charge loss effect from the thinner top oxide of the ONO layer of the SONOS devices is observed. On the other hand, as P/E cycle number increases, significant electron trapping events occur in the FG devices, resulting in shrinkage of threshold voltage window. In addition, interface states generated during programming procedure are observed for the two types of devices, especially for the SONOS devices. Although channel initiated secondary electron (CHISEL) programming of the SONOS devices would greatly increase interface state density, and result in subthreshold swing (SS) and transconductance (GM) degradation, our results indicate that an acceptable threshold voltage window retains even after a great number of P/E cycles.