絕緣層上矽金氧半場效電晶體元件特性之模擬與分析

Abstract

本論文的主要研究在於設計、模擬以及分析絕緣層上矽金氧半場效電晶體(SOI MOSFETs)元件特性，尤其針對摻雜濃度梯度、空間層長度、閘極長度以及矽薄膜層厚度等四項參數探討其元件特性、導通以及截止電流，並針對國際半導體技術藍圖制定協會的高效能以及低功率之規範討論各項參數對元件效能之影響。我們發現摻雜濃度梯度與空間層(spacer)長度對元件效能互有消長之關係，且其影響較閘極長度以及矽薄膜層厚度所造成的影響為小。縮短閘極長度的確可提升元件的操作的速度，但漏電流效應更為明顯，反而不利於元件效能之提升。而矽薄膜層的厚度，在高效能以及低功率的表現上皆為元件性能提升的主要關鍵。

In this study, we designed, simulated and analyzed the device characterization of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The effects of doping concenteation gradient,spacer length, gate length, and silicon body thickness to the device performance are investigated by comparing the on- and off-currents of simulated SOI MOSFETs with the high performance (HP) and low operating power (LOP) specifications of International Technology Roadmap for Semiconductors (ITRS). We found the effects from spacer length and doping concenteation gradient can be trade-off and their effects were much less than those from the other two parameters. Scaling down the gate length can increase device speed but the accomapnied large leakage current may rule out the merit of speed improvement. After all, the thickness of silicon body is the key point to device performance enhancement based on both HP and LOP specifications.