BCD製程之SOI-LDMOS製程與元件模擬

Abstract

在近代半導體元件與製程的研究與發展中,橫向雙擴散金屬氧化物半導體（Lateral Double-Diffused Metal-Oxide-Semiconductor, LDMOS）由於易於與低電壓的積體電路集成，以形成具有高壓功能的積體電路（High Voltage Integrated Circuits, HVIC）和智能電源管理積體電路（Smart Power Management Integrated Circuits, SPMIC），故已逐漸引起廣泛的探討與研究。 但是,卻少有研究與文獻同時探討製程與元件模擬.因此,本論文將利用製程模擬(SProcess)與元件模擬(SDevice)來設計與探討一個高壓(120 V)的LDMOS元件. 本論文主要是探討與研究BCD（Bipolar-CMOS-DMOS）製程中的LDMOS，而其結構與參數則是建構於矽絕緣體上(Silicon On-insulator, SOI)。而此SOI-LDMOS，是建構在0.8 µm SOI-BCD的製程平台上，其工作電壓為12 V (Vgs)至120 V (Vds)的高電壓元件，而其具備的中等溝槽局部氧化層結構(Medium Trenched Isolation Local Oxidation of Silicon , MTI-LOCOS)被應用於此製程中，以降低寄生效應。 經由Synopsys公司的Sentaurus模擬工具的研究，我們建立了一個系統性的架構來模擬SOI-NLDMOS的製程與結構，並對此元件的電性做深入的探討與研究。這些電性包括臨界電壓，飽和電流，擊穿電壓和自熱(Self-heating)特性等。 SOI-LDMOS雖然具有耐高壓、低漏電流，高運算速度和抗輻射等優點，然而，由於SOI-LDMOS掩埋氧化層的導熱性較差，導致元件的自熱效應。而此自熱效應將造成漏極電流的退化。 在本文中，我們亦將在使用不同的載子傳輸模型(carrier transport models )下,對SOI-LDMOS的自熱效應進行探討。此研究的結果顯示，元件使用不同的載子傳輸模型，對元件模擬的電熱特性與精準度有相當大的差異。根據研究結果，我們在元件結構上做一些改進，以提高元件的熱效率和崩潰電壓，並對此進行探討。

Interest in lateral diffused metal-oxide semiconductors (LDMOSs) has been growing, due to their ease of integration with low voltage circuitry to form high voltage integrated circuits (HVICs) and smart power management integrated circuits (SPMICs). Despite considerable researches, few are found to have explored and documented the process and device simulation at the same time. This study adopted the process simulator SProcess and the device simulator SDevice to design a high-voltage (>120 V) LDMOS. We investigated an LDMOS structure fabricated using the Bipolar-CMOS-DMOS (BCD) process based on silicon on-insulator (SOI) substrates. This research outlines the development of SOI-LDMOS based on 0.8 µm BCD technology with operating voltage from 12 V (Vgs) to 120 V (Vds). We also proposed a novel medium trenched isolation local oxidation of silicon (MTI-LOCOS) process to reduce the parasitic effect. Through research using Synopsys Sentaurus simulation tools, we developed a system to simulate the processes involved in device fabrication of SOI-NLDMOS devices. We aim is to understand the effects of process parameters on SOI-LDMOS device characteristics by establishing a simulation methodology calibrated by experimental data. These characteristics included threshold voltage, saturation current, breakdown voltage and self-heating characteristics. SOI-LDMOS devices have strong ability in sustaining high drain voltage with low power leakage, high operation speed and anti-radiation features. However, SOI-LDMOS transistors suffer from self-heating effect due to poor thermal conductivity of the buried oxide. This effect can cause the degradation of drain current at certain device bias condition. In this thesis, the self-heating effects within SOI MOSFETs were explored using different carrier transport models. The results of this investigation reveal considerable variations in electrical characteristics and temperature within the device during operation. Based on the results mentioned above, we modified some structures to improve the thermal efficiency and breakdown of the device were explored.