Characterization and SPICE Modeling of High Voltage LDMOS

Abstract

隨著半導體產業的發展，高功率元件經常被應用在許多電力電子方面。LDMOS(平面二次擴散之金氧半場效電晶體)通常在高壓積體電路中作為驅動元件，這可歸功於它的平面結構。由於缺少內建的高壓元件模型，因此功率元件的模擬通常是利用子電路（sub-circuit）的模擬方法。本論文我們將利用子電路的方式提出一套可以模擬LDMOS的方法。

首先，我們將探討LDMOS與MESDRIFT（比LDMOS多一個接觸點佈值）的特性；其中包括準飽和、衝擊離子化的機制以及LDMOS與MESDRIFT的特性比較。藉由元件模擬軟體TCAD的使用，我們可以更瞭解元件內部操作原理與過程。接著，LDMOS完整的模型翠取流程將會被討論；其中包含了利用各種測試結構翠取出來的MOS模型以及藉由數值分析的Vk公式推導之RD電阻模型。最後，LDMOS產生的自我熱效應（Self-Heating Effect）將會藉由TCAD模擬來探討元件內部溫度分佈情況，為了更進一步的瞭解SHE，我們建立一套微秒暫態量測電路（micro-second transient measurement circuit），藉著此電路的輔助，我們將得以觀測脈衝長短與功率大小相依的熱造成的電流下降程度議題，並提出兩套簡單模型來描素SHE的行為。

根據我們的研究，可以歸納出以下結果：KPC的元件與LDMOS的特性最為相近，因此利用Vk的概念，可被選來作為模擬的測試結構；利用反算的電阻RD可以來彌補在高汲極與高閘極電壓狀況下，模擬與量測不準的情形；SHE是受施加於元件的脈衝長短與功率大小所影響（脈衝愈長，功率愈大，則SHE就愈明顯）；最後，考慮準飽和效應的LDMOS SPICE模型將會在本論文中完成。

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely applied to power electronics owing to great semiconductor industry. LDMOS (lateral Double-Diffused MOSFET) is usually the driver component in high voltage integrated circuits, thanks to its planar structure. Because of the lack of suitable built-in HV model, the sub-circuit modeling is usually used for the simulation of the power devices. In this thesis, we propose a method to modeling LDMOS by sub-circuit method.

First, we engage in the characteristics of LDMOS and MESDRIFT devices which have an extra contact implant comparing to LDMOS, including the quasi-saturation, impact ionization mechanism and the comparison between LDMOS and MESDRIFT device. We can make it clearer that the operation principle and process inside LDMOS while device is under operation. Then, macro model extraction flow of LDMOS including MOS model which can be extracted from various test structures and RD model which can be modeled through Vk formula derivation in numerical method will be discussed. Finally, self-heating effect will be investigated by TCAD simulation for temperature profile and by pulsed-gate experiment for the influence of heat which is dependent on pulse width and power. Two simple models are also proposed to describe the behavior of SHE.

According to our study, we can conclude that: KPC device has the best match to LDMOS, so it is chosen to modeling LDMOS with the concept of intrinsic drain voltage, Vk; using reverse calculated RD can modify the mismatch between simulation and measurement of LDMOS at high drain and gate bias; SHE is affected by pulse width and the power applied to device (the longer pulse width, the larger power, and then the more serious SHE); finally, SPCIE model of LDMOS considering quasi-saturation is completed.