高電壓橫向擴散金氧半電晶體中暫態熱載子效應與元件模型之探討

Abstract

隨著電源管理日趨重要，橫向擴散金氧半導體場效電晶體(LDMOS)於高電 壓整合型電路中的使用也日趨廣泛。在高功率的操作下，熱載子引發的可靠性問 題及元件模型的建立仍然是最大挑戰。 本篇論文將針對LDMOS 的可靠度與元件模型的建立做一系列探討。首先， 吾人提出一個具有特殊接觸電極的LDMOS 結構，藉以量測LDMOS 中通道 (channel)部分的內部電壓(internal voltage)、電流、與低頻雜訊。兩個利用此種特 殊結構的例子將在第二章中被討論；一個是對自我加熱效應(self-heating effect) 的研究，另一個是對通道電流與LDMOS 電流的特性分析。在自我加熱效應的研 究中，吾人提出一個以內部電壓為觀察指標的研究方式，觀察到自我加熱效應所 引發的暫態電壓改變將呈現兩段式變化。我們的研究也顯示出，內部電壓量測法 將比傳統電流量測法更有效率，並能更清楚得到所需要的熱時間常數。在另一個 例子中，此特殊結構將用來研究通道與LDMOS 間的特性。電流與低頻雜訊在通 道中與在LDMOS 中的特性將被研究。我們的研究顯示，在低閘極偏壓下，汲極 電流與汲極低頻雜訊主要是由LDMOS 中的通道所決定，這也暗示了一個新的元 件模型建立方法與熱載子(hot carrier)特性分析方法。 ii 在第三章中，針對熱載子效應所導致的氧化層傷害，吾人提出一個新式三段 式電荷幫浦(three-region charge pumping)的量測方法加以研究。利用此方法，我 得以確認不同傷害模式下的氧化層損傷位置，並可以進一步知道所產生的損傷缺 陷特性。我們的研究結果顯示，在最大閘極電流(max. IG stress)模式下，將導致 最大的汲極電流與次臨限區斜率(subthreshold slope)的退化，退化的原因為通道 區的表面缺陷(interface trap)產生與鳥嘴區(bird’s beak region)的負電荷量(negative oxide charge)累積，其產生的速度將可從三段式電荷量測幫浦中個別萃取。同時， 我們也將利用二維元件模擬與低頻雜訊量測方法進一步確認實驗結果。 經由前面章節的了解，在第四章中，吾人將利用特殊結構研究自我加熱效應 所引發的暫態熱載子效應(transient hot carrier effect)。同時，利用二維元件模擬驗 證實驗結果，並用來分析交流頻率與元件退化間的關聯性。吾人研究結果發現， 熱載子效應在交流偏壓下的電流退化，將比直流偏壓下的電流變化更為嚴重，其 原因在於自我加熱效應的消失將造成熱載子的增加。 最後，吾人發展出一個雙組合元件模型(a two-component device model)，用 來描述LDMOS 的電流特性，並將模擬自我加熱效應所引發的內部電壓改變。此 LDMOS 模型將使用一種新的模型建立方法，以低閘極/高閘極電流分別建立通道 區與淡摻雜區(drift region)的模型。並利用內部電壓控制有/無自我加熱效應下的 汲極電流。經由比較後發現，我們的模型在所有的操作電壓下均可以準確的預測 汲極電流，這範圍包含次臨限區(subthreshold)到臨限區以上(super-threshold)、有 自我加熱情形及無自我加熱情形都可準確描述。

Lateral diffused MOS (LDMOS) are extensively used in today’s high-voltage integrated circuits, particularly where power handling is important. Hot carrier induced reliability concerns and device modeling problems in such high power operation are being aroused. The objective of this dissertation is to investigate both reliability and device modeling issues in LDMOS transistors. First of all, a novel LDMOS structure incorporating an additional metal contact in the drift region is fabricated, which allows us to probe internal voltages, currents, and flicker noise in the channel-part of a LDMOS. Two examples of making use of this structure are presented in Chapter 2; one is a study for self-heating effect and the other is a characterization between channel and LDMOS currents. In the self-heating study, an internal voltage method to characterize self-heating effect is proposed. We find that a self-heating induced internal voltage transient exhibits two stages. The time constants of self-heating are iv measured. Our study shows that the internal voltage method is more sensitive to self-heating than a conventional drain current method in a LDMOS. In the other example, the metal contact structure is used to investigate the channel and the LDMOS characteristics. Current and flicker noise in the channel and in the LDMOS are measured. Our experiments show that both drain current and drain flicker noise at low-VG regime are major determined by the channel-part of a LDMOS, which imply a new extraction method for device modeling and a characterization technique for hot carrier effects. In Chapter 3, hot carrier stress induced oxide degradation in n-LDMOS is investigated by using a novel three-region charge pumping technique. This technique allows us to locate oxide damage area in various stress modes and gain insight into trap creation properties. Our characterization shows that a max. IG stress causes a largest drain current and subthreshold slope degradation because of both interface trap (Nit) generation in the channel region and negative bulk oxide charge (Qox) creation in the bird’s beak region. The density of Nit and Qox can be separately extracted from the proposed charge pumping method. A numerical device simulation and drain flicker noise are performed to confirm our result. Based on the understanding of Chapter 3, self-heating induced transient hot carrier effects are investigated in Chapter 4 by using the metal-contact structure introduced in Chapter 2. The AC stress-frequency dependence of device degradation is characterized and evaluated by a two-dimensional numerical simulation. Our result shows that drain current degradation in AC stress is more serious than in DC stress because of the reduction of self-heating effect. Finally, a two-component device model including self-heating induced internal voltage transient in a LDMOS is developed. A new modeling method for the channel/drift regions is proposed by fitting a low-VG/high-VG drain current. Our v modeling method uses an internal voltage to control drain current in self-heating and in non-self-heating conditions. A comparison with dc measurements shows that our model provides an accurate description in all regimes of operation, ranging from subthreshold to super-threshold, for both self-heating and non-self-heating conditions.