複晶矽薄膜電晶體製程效應與偏壓溫度不穩定性之研究

Abstract

在本論文中，首先，我們在閘極氧化層沉積後利用高溫通氧的條件來提升閘極氧化層的可靠度。另外我們在成長薄膜電晶體通道之前，運用低溫低壓的條件預沉積一氧含量較高的薄膜矽襯墊層，因為較高的氧含量會抑制固相再結晶 (Solid-Phase Crystallization) 時的成核。藉由這個方式，可以在通道中形成更大的晶粒尺寸(Grain size) ，藉而得到更高的載子場效遷移率。我們發現，特別是在小尺寸的元件中，預沉積矽襯墊層有效的提高複晶矽薄膜電晶體 (poly-Si TFTs) 的場效遷移率、驅動電流，並有效降低閘極引發汲極漏電流 (GIDL current) 以及次臨限擺幅 (Subthreshold Swing)。再者藉由使用預沉積矽襯墊層，也改善了元件的可靠度以及均勻性。 接著，我們分別對p-通道複晶矽薄膜電晶體進行負偏壓溫度不穩定性 (Bias Temperature Instability) 之研究，以及對n-通道複晶矽薄膜電晶體進行正偏壓溫度不穩定性對於元件可靠度的影響之研究。我們分別探討不同的溫度以及所施加的偏壓，對於上述兩種偏壓溫度不穩定性在元件退化所造成的影響。實驗結果顯示，正、負偏壓溫度不穩定性在低溫複晶矽薄膜電晶體中會有著不同的退化機制，但對於元件可靠度都有很大程度的影響。 最後，我們探討動態負偏壓溫度不穩定性對於p-通道複晶矽薄膜電晶體可靠度的影響。藉由不同的偏壓方式，我們可以發現元件在進行負偏壓溫度不穩定性之測試時所產生的缺陷狀態，會在正閘極偏壓下被修補。在CMOS反向器使用中，這樣的修補會使得元件使用期限大幅提升，藉由使用動態負偏壓溫度不穩定性測試，可以得到更貼近現實使用下的元件使用期限。

In this thesis, first, we used a post-anneal procedure with oxygen ambient after the deposition of gate oxide. Poly-Si TFTs with such a post-anneal procedure have enhanced electrical characteristics and much improved reliability. In addition, we deposited a buffer amorphous Si (a-Si) layer under both low temperature and pressure before the deposition of the channel. Si layers grown under this condition would have higher oxygen concentration, and this would suppress the nucleation mechanism under solid-phase crystallization (SPC). With the buffer Si layer, the bi-layer Si, with a-Si layer beneath the poly-Si channel after the SPC process, would have larger grain size and lead to enhanced performance. Measurements revealed that the devices’ electrical characteristics are improved not only in field effect mobility and gate-induced-drain leakage (GIDL) current, but also in driving current and subthreshold swing. Moreover, the ability of immunity against hot-carrier injection and device uniformity are improved. Then, we studied the degradation mechanisms of negative bias temperature instablity (NBTI) and positive bias temperature instability (PBTI) in p- and n-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs), respectively. As the stress gate voltage increases, the absolute values of threshold voltages shift (|ΔVth|) increase under NBTI and PBTI stress. When the stress temperature is raised, the |ΔVth| increases under NBTI stress but almost unchanged under PBTI stress, indicating that the degradation mechanisms of NBTI and PBTI are different. Furthermore, the field-effect mobility is rarely changed under NBTI stress; however, it increases under PBTI stress. From the experimental results, we demonstrated that the NBTI degradation can be explained by the diffusion-controlled electrochemical reactions, while the PBTI degradation is caused by charge trapping in the gate dielectric. Finally, we investigated the impact of dynamic NBTI in p-channel LTPS TFTs. In conventional NBTI studies, static gate bias is used to determine the lifetime of p-channel LTPS TFTs. However, DNBTI in p-MOSFETs showed that the lifetime was much longer than that derived from static NBTI stress because of the passivation effect. We found that LTPS p-TFTs have passivation effect under positive gate bias during a stress-passivation-stress process. As a result, we would underdetermine the true lifetime of LTPS p-TFTs when we use static NBTS to derive it. Therefore, it is necessary to use DNBTS to simulate the bias condition of their really applications.