適用於靜電放電電路模擬之防護元件模型研究

Abstract

隨著半導體產業的發展，元件尺寸持續的縮小化，此時靜電放電對元件的影響日益嚴重，成為元件可靠度的主因，由於靜電放電的破壞會造成元件功能上永久性的損壞，因此必須設計靜電放電防護電路在積體電路上，才可以避免靜電放電的破壞。然而電路上幾乎沒有多餘的空間來擺放靜電放電防護電路，所以靜電放電防護電路必須要有最佳化設計，但現今工業靜電放電電路設計仍以試誤法為主，這樣會導致資源上的浪費。 本文主要建立一個以SPICE為主的靜電放電防護電路，透過這樣的電路模擬與分析，進而減少設計上的時效。由於靜電放電是一種快速且具有高電流的放電模式，因此在靜電放電防護電路上的元件，必須選擇具有高電流導通性與低崩潰電壓等特性。在我們的靜電放電防護電路上的保護元件，以Diode、BJT和NMOS為主，我們將對這些元件進行量測並模型化，使其能夠應用在靜電放電防護電路模擬中。實驗上，以TLP(Transmission Lines Pulse)系統對靜電放電防護電路進行量測，此量測結果將與我們模擬結果進行比對，並以HBM(Human Body Model)與MM(Machine Model)進行分析。

In addition to high performance, low cost, and low power, reliability is also an important issue in the development of VLSI technologies. Damage caused by ESD (Electro-static Discharge) is a serious threat to VLSI reliability. It is well know that ESD failures constitute a major portion of customer returns, so it is important to provide ESD protection in the IC chip against ESD damages

If an ESD stress current flows into internal circuits, it can cause internal damage. Therefore, it is necessary to predict ESD immunity, which depends on the circuit design and layout. At present, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. ESD simulations for the protection circuits are effective for solving this problem. The purpose of thesis is to construct an ESD circuit simulation system based on the SPICE circuit simulator. Through the SPICE simulation, we can reduce design cycle. In our ESD protection network, we choose the diodes, BJT, and NMOS as ESD protection devices. We will model those devices corresponding to the experiment and implement the models to the ESD circuit simulation system.