标题: 适用于静电放电电路模拟之防护元件模型研究
Study on Modeling of ESD Protection Devices for Circuit-Level ESD Simulation
作者: 林哲仕
Che-Shih Lin
汪大晖
Tahui Wang
电机学院微电子奈米科技产业专班
关键字: 静电放电;骤回崩溃;ESD;snapback breakdown
公开日期: 2006
摘要: 随着半导体产业的发展,元件尺寸持续的缩小化,此时静电放电对元件的影响日益严重,成为元件可靠度的主因,由于静电放电的破坏会造成元件功能上永久性的损坏,因此必须设计静电放电防护电路在积体电路上,才可以避免静电放电的破坏。然而电路上几乎没有多余的空间来摆放静电放电防护电路,所以静电放电防护电路必须要有最佳化设计,但现今工业静电放电电路设计仍以试误法为主,这样会导致资源上的浪费。
本文主要建立一个以SPICE为主的静电放电防护电路,透过这样的电路模拟与分析,进而减少设计上的时效。由于静电放电是一种快速且具有高电流的放电模式,因此在静电放电防护电路上的元件,必须选择具有高电流导通性与低崩溃电压等特性。在我们的静电放电防护电路上的保护元件,以Diode、BJT和NMOS为主,我们将对这些元件进行量测并模型化,使其能够应用在静电放电防护电路模拟中。实验上,以TLP(Transmission Lines Pulse)系统对静电放电防护电路进行量测,此量测结果将与我们模拟结果进行比对,并以HBM(Human Body Model)与MM(Machine Model)进行分析。
In addition to high performance, low cost, and low power, reliability is also an important issue in the development of VLSI technologies. Damage caused by ESD (Electro-static Discharge) is a serious threat to VLSI reliability. It is well know that ESD failures constitute a major portion of customer returns, so it is important to provide ESD protection in the IC chip against ESD damages

If an ESD stress current flows into internal circuits, it can cause internal damage. Therefore, it is necessary to predict ESD immunity, which depends on the circuit design and layout. At present, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. ESD simulations for the protection circuits are effective for solving this problem.
The purpose of thesis is to construct an ESD circuit simulation system based on the SPICE circuit simulator. Through the SPICE simulation, we can reduce design cycle. In our ESD protection network, we choose the diodes, BJT, and NMOS as ESD protection devices. We will model those devices corresponding to the experiment and implement the models to the ESD circuit simulation system.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009394507
http://hdl.handle.net/11536/80337
显示于类别:Thesis