針對低功率設計的新匯流排編碼技術

Abstract

對於低功率設計來說，降低匯流排的電位變化數目是個相當重要的議題。在本篇論文中，我們提出一種新的匯流排編碼技術來降低匯流排電位變化數目，此方法根據資料特性動態地選擇identify、invert或xnor運算來執行匯流排編碼。我們比較了BI、BITS、hihrTS以及EXODUS等編碼方式，以隨機亂數、不同形式的音訊、影像以及經過DCT轉換的影像等檔案來做實驗。之後我們以VHDL來實現我們的架構以及論文中所提及的方法，得到編碼器/解碼器所需的功耗。根據匯流排的動態功耗計算方式，我們由實驗結果推導並比較以不同方法編碼時的實際功耗。最後我們以IEEE 802.16e基頻傳送端為例，利用CoWare Platform Architect建立ARM-Based系統晶片虛擬平台並以本文所提及之編碼方式來模擬。

Reducing the number of bus transitions is an important issue for low power design. In this thesis, we propose a new bus encoding scheme to reduce bus transitions. This scheme dynamically adapts to data patterns and applies identity, invert and xnor bus encoding operations accordingly. We compared our encoding scheme with BI, BITS, hihrTS and EXODUS encoding schemes. We perform experiments with random data streams, different types of audio input, image files and DCT-transformed image files. Then we implement our structure and all mentioned schemes in VHDL and obtain the power consumption of encoder/decoder. According to the dynamic power consumption of bus model, we calculate and compare the power consumption for all experiments. Finally we use CoWare Platform Architect to build an ARM-Based SoC virtual platform and implement all encoding schemes. The study case is IEEE 802.16e baseband TX.