應用於週期精確指令集模擬器之高效率SystemC建模技術

Abstract

隨著晶片設計複雜度日趨複雜，電子系統層級設計正成為主流的設計方法。SystemC是一種基於C++，並支援各種虛擬層級，且廣泛應用於建模及驗證的電子系統層級設計語言。 本論文提出一應用於週期精確指令集模擬器之高效率SystemC建模技術。以32位元精簡指令集嵌入式處理器為例，我們使用SystemC將該處理器建模於兩個不同的虛擬層級—暫存器傳輸層級以及週期精確行為層級。該處理器所採用之指令集架構為ARM指令集(第四版)。我們測量所提出的模型及參照之Verilog模型之模擬時間來作效能比較。實驗數據顯示，我們提出的週期精確行為層級指令集模擬器之效能比參照之Verilog模型快十倍。

With the increase of the complexity of chip design, Electronic System-Level (ESL) design is becoming a mainstream design methodology. SystemC, a language based on C++, supports a broad range of abstraction levels and views, and is widely used as an ESL language both for modeling and verification. In this thesis, an efficient SystemC modeling technology for cycle-accurate instruction set simulator (ISS) is presented. A 32-bit RISC embedded processor core is modeled in SystemC at two different abstraction levels, the register-transfer level (RTL) and the cycle-accurate behavioral level, as an evaluation case. The instruction set architecture (ISA) of the modeled processor core adopts ARM ISA Version 4. We measure the simulation time of the proposed models and the reference Verilog model for performance comparison. The experimental results show that our proposed cycle-accurate behavioral level ISS is ten times faster than the reference Verilog model.