時空籬柵碼之解碼器設計與實現

Abstract

由於通訊結合多媒體服務需求的急遽成長，無線通訊(例如第三代行動通訊系統與無線區域網路)朝向高資料量傳輸發展已成為不可避免的趨勢。時空籬柵碼，結合錯誤更正碼，調變以及傳送和接收分集，可以有效的降低無線通訊環境的衰減效應。因為時空籬柵碼的編碼結構與迴旋碼相似，同樣由暫存器組成，所以產生相似的籬柵圖可用維特比演算法做解碼。一般而言，解碼器架構是由支計量單位，加-選擇-比較單位以及存活記憶體單位所組成。雖然加-選擇-比較單位是維特比演算法主要的計算單位，但是存活記憶體單位確是解碼器架構實現到硬體上需要做最多的考量，因為佔據的晶片面積，耗電量以及影響解碼速度都是最大的。本論文針對解碼器硬體架構，包括傳統存活記憶體管理架構，高速VLSI追溯解碼架構和混合式存活記憶體管理架構的優缺點做出分析。並提出結合改良式暫存器交換和排列網路電路的架構。最後用軟體模擬以及實現在FPGA硬體上。

With the integration of internet and multimedia applications in next generation wireless communication, the demand for faster and higher data rate communication service becomes inevitable. One practical way to increase the capacity of wireless channel is by employing multiple antennas to create multiple-input and multiple-output (MIMO) channel system. The coding technique that employs multiple antennas is space-time coding. Space-Time Trellis Codes, joins the design of error control coding, modulation, transmit and receive diversity, is an effective signaling scheme able to combat the effect of fading in wireless environment. The decoder for such codes employs the Viterbi algorithm to perform maximum likelihood decoding since the encoder structure consists of shift registers that can be interpreted to trellis diagram as in convolutional codes. The decoder architecture consists of branch metric, add-select-compare, path metric memory and survivor memory units. Although the add-compare-select unit is the main component that performs the Viterbi algorithm, the survivor memory unit requires more attention because it occupies most of the decoder chip area, power consumption and is a critical data-processing component that affects the speed of decoder. The goals of this thesis are to develop a survivor memory unit that can achieve the advantages of low latency, low hardware complexity, and reduced chip area. The proposed decoder architecture is implemented in both software simulation and FPGA implementation.