無外部電容的CMOS低壓差線性穩壓器

Abstract

近年來，由於可攜式電子產品的快速發展，開發低功耗的電路來延長電池壽命己成為主要的研究主題。同時為了達到產品的輕薄、短小，將電路積體化及減少外部元件的使用已經是必要的趨勢。 一般的電源管理系統通常會包含幾組低壓差線性穩壓器及交換式的直流轉換器。傳統的低壓差線性穩壓器需要一個很大的輸出電容大約幾微法拉，如此大的電容並不容易作在IC內部，並且需要佔據較大的電路板面積及成本。本論文的目標是設計一個無需外部電容的低壓差線性穩壓器，此低壓差線性穩壓器是架構在三級的放大器設計，能同時兼顧穩定度、精準度、暫態響應及其它各項效能。所設計的規格是最大負載電流100mA，輸入電壓在1.5V~4.5V，輸出電壓在1.3V, ，Dropout Voltage 在200mV，使用TSMC 0.35μm 2P4M CMOS製程，包含參考電壓源僅消耗46μA的靜態電流。實驗的結果証明所實作的低壓差線性穩壓器在穩定度及暫態響應都符合所預期的規格。因此，此低壓差線性穩壓器適合於SOC的環境使用。

In the recent years, developing of low power circuits to extend battery life has become a critical research topic due to explosion growing of portable electric devices. In order to make products smaller and thinner, this is a necessary trend to integrate the circuit and reduce the external component. A power management system usually contains serval LDO regulators and switching regulators.The conventional LDO voltage regulator requires a very large output capacitor in the single microfarad range.Large microfarad capacitors can not easy integrated in IC, and take over a large area of PCB, consuming cost. The target of this paper is to design a low dropout linear voltage regulator without external capcitor. This LDO is based on three stage amplifiers design, and also consider the stability, resolution, transient response and other performances. The design of specification is shown is the following: The maxmium load current is 100mA. The input voltage is ranged from1.5V to 4.5V. The output voltage is 1.3V. The dropout voltage is 200mV. The quiescent current is consuming only 46uA containing the bandgap reference. This LDO is fabricated by TSMC 0.35um 2P4M process. Experimental results show that the proposed capacitor-free LDO voltage regulator is achieved the expected specification of stability and transient response.Thus, the proposed capacitor-free LDO voltage regulator is suitable for SoC solution.