高速輸出入介面電路之靜電放電防護設計

Abstract

本篇論文主旨在設計適用於高速輸出入介面之靜電放電防護電路。隨著互補式金氧半元件越來越薄的閘極氧化層和高速輸出入介面電路的工作頻率越來越快的情況下，如何在高速的頻段中設計即時有效的靜電放電防護，並降低由靜電放電防護電路所導致的負面影響，是一個相當大的挑戰。本論文所提出的靜電放電防護方式既可以達到商業規格的靜電放電耐受度要求，也可有效地降低靜電放電防護元件產生的寄生效應對高速輸出入介面電路性能的影響。本篇論文分為二大部分，透過理論的推導以及實驗晶片的量測，來驗證適用於高速輸出入介面的靜電放電防護設計。 本論文的第一部分是在0.13微米CMOS製程中，藉由高頻量測系統、傳輸線脈衝產生系統(Transmission Line Pulsing System, TLP)，以及靜電放電耐受度量測系統，分別對不同尺寸的靜電放電防護元件進行測試。利用雙埠接地-訊號-接地(Ground-Signal-Ground, GSG)的晶片上(On-Wafer)量測方式萃取靜電放電防護元件的高頻特性，經過分析及計算後，已建立符合高速輸出入介面電路使用之靜電放電防護元件資料庫，可提供實際應用上最適合的靜電放電防護元件組合。 本論文的第二部分，提出適用於高速輸出入介面電路的靜電放電防護設計。憑藉本研究建立的資料庫，可適當地選擇符合需求的靜電放電防護元件尺寸，此方式既可滿足商業規格的靜電放電耐受度要求，並且可以將靜電放電防護元件之寄生效應對核心電路的衝擊降至最低。此外可將靜電放電防護元件置於銲墊(Pad)底下，除了可以減少靜電放電防護元件佔用的晶片面積，還可利用銲墊寄生電容與靜電放電防護元件寄生電容相互串聯的效應，進一步降低輸入輸出接點的寄生電容值。 本論文已經透過實驗晶片的量測，成功驗證本研究所提出的高速輸出入介面電路之靜電放電防護設計架構，實驗結果證實此設計適用於高速輸出入介面電路的靜電放電防護設計。

This thesis focuses on the ESD protection design for high-speed input/output (I/O) interface circuit. The gate oxide of the MOSFET transistor becomes thinner as the CMOS technology scales, which enables the high-speed I/O interface circuits with higher operating frequency. Unfortunately, there exists a challenge to design an ESD protection circuit with satisfactory ESD robustness and low parasitic effects to the gigahertz high-speed I/O circuit. This thesis presents a design methodology to design the ESD protection circuit for gigahertz high-speed I/O circuits with high ESD robustness and low parasitic capacitance. There are two major designs in this thesis, in first part, the two-port ground-signal-ground (GSG) measurement setup in the radio-frequency band (~GHz) is used to measure the high-frequency characteristics of ESD devices and the TLP measurement system is used to measure the ESD robustness of the ESD devices in a 0.13-□m CMOS process. Therefore, the relationship between the high-frequency characteristics and ESD robustness under different ESD device dimensions can be obtained. The second part presents the most suitable ESD device for gigahertz high-speed applications based on the database which had been established in the first part. With the database, the optimal ESD device dimensions can be obtained as long as the requirement of parasitic capacitance and ESD robustness are determined. Besides, placing the ESD protection device under the bond pad can further reduce the parasitic capacitance and the total chip area. The test devices and the ESD protection design in this thesis have been fabricated in a 0.13-□m CMOS process, and the experimental results have shown that this ESD protection design is suitable for gigahertz high-speed I/O interface circuits.