內建自我測試電路之管線式類比數位轉換器

Abstract

近年來由於積體電路製程的進步以及離散時間數位信號處理技術的發展，同時，在解析度、速度、和功率消耗的彈性，管線式類比數位轉換器被廣泛的應用在許多不同的領域。在傳統轉換器的靜態測試中，測試時間消耗及測試設備的需求是主要成本。在這篇論文裡，我們實現一個管線式類比數位轉換器以及其內建自我測試電路。 利用單一管線級的優點，我們使用後一級的比較器來掃描前一級的轉換曲線，掃描的結果配合信心區間的機率分析，可以得到單一級的增益誤差以及偏移誤差；我們設計一個8位元每秒100百萬取樣的管線式類比數位轉換器來驗證這個新的測試方式，而這個轉換器由七個每級1.5位元解析度和1位元解析度的最後一級組成。 所提出的電路架構將被實現在TSMC 1P6M CMOS 0.18 m的製程，其晶片面積為 (不包含PAD)，在正常模式輸入信號是20.9百萬赫茲的情況下，最高SNDR是47.09dB，總共的功率消耗為 110 mW；在自我測試模式下，刻意再第一二級加入已知的增益誤差，讓內建自我測試電路來量測，而其結果符合已知的增益誤差量，同時利用軟體Matlab來消除已知的增益誤差。

New CMOS and digital signal processing techniques have a great variety of applications in recent years. Pipelined ADC is wildly utilized for its flexibility in speed, resolution, and power. In traditional converter’s static testing time consumption and hardware overhead of test equipment are still the prime concerns. In the thesis, a simple built-in self test is proposed for pipelined analog to digital converters. By taking the advantages of the structure in pipelined stage, we use the next stage comparators to scan the transfer curve of the previous stage. The stage gain error and offset error can be estimated. With certain confidence interval analysis reliable results can be achieved. A 8-bit 100MS/s pipelined ADC is realized to verify the algorithm. It is made of seven stages of 1.5-bit sub-converters and an 1-bit back end stage. The proposed pipelined ADC and BIST circuit are designed using TSMC 1P6M CMOS process with an active die area of . In normal operation the peak SNDR is with the input signal frequency of . The total power consumption of the proposed modulator is . In BIST mode, with intentional mismatch added into stage one and stage two, gain errors can be estimated correctly. Finally the Matlab is used to correct the error.