側向成長複晶矽薄膜電晶體之可靠度研究

Abstract

由於複晶矽薄膜電晶體能夠整合週邊驅動電路且因複晶矽元件應用於面板週邊驅動邏輯電路時，需要考量到複晶矽元件可靠度的問題，本論文中有探討新型側向結晶方式Sequential Lateral Solidification (SLS)所製作出的複晶矽元件其電性與可靠度，由材料分析上可發現SLS所產出的晶粒尺寸比一般傳統excimer雷射來得大，我們可以將SLS晶界分為二種：一為主晶界(main-GB)，二為次晶界(sub-GB)，主晶界的特徵在於其晶界走向垂直元件通道方向，並且在複晶矽薄膜結構中為一突起(protrusion)；次晶界則是平行通道方向且較平坦，論文中挑選兩種較明顯對比之電晶體進行分析，GB TFT為一含有主晶界在通道中央，NBG TFT中則僅有次晶界存在，由電晶體參數萃取可發現NGB TFT其起始電壓、次臨界撥動、載子遷移率都比GB TFT優良。而為了應用於驅動邏輯電路，針對此種複晶矽薄膜電晶體作ㄧ系列的AC gate bias stress劣化機制的探討。複晶矽的晶界視為一缺陷捕獲區，當捕獲住載子後，會再此區域型成一高電場區， 並由模擬軟體的結果得知，再晶界處與沒有晶界的薄膜相比會累積更多的載子，而此過多的載子在AC gate bias stress下會導致更顯著的劣化。而此區域型成的高電場若在元件中所扮演的腳色不在是對稱型時，會使得元件特性因電場增強的效應下變的容易開啟，但相對的晶界在高電場下會使得漏電特性變的更加嚴重。除此之外，也針對了AC bias的電壓波形分成四個部份個別研究，劣化的機制主要跟電壓由高電位到低電位所需的時間，和保持在低電位所給的時間有關。

On study the grain boundary (GB) effects, the comparison of electrical stability between GB and NGB TFT has been demonstrated. The NGB TFT owns superior conducting ability than the GB TFT which contains a 100-nm trap-numerous region at the middle of the channel. The influence of protrusion grain boundary on the degradation of crystallized laterally grown Polycrystalline Silicon Thin Film Transistors is investigated. Nevertheless, the distinct electrical behaviors of the TFTs were demonstrated under the AC gate bias stress. Due to the existence of protrusion in the channel, GB TFT shows weaker endurance against the AC gate pulse stress than that of NGB TFT. The magnitude of the vertical field at the protrusion is stronger than the other regions in GB TFT. The strong electric field would lead to the state creation and charge trapping at the protrusion and reduce the device’s electrical performance. We investigate the basic electric characteristics of the poly Si TFT which has the different of GB position in the channel with respect to the source junction. The degradation of TFT with protrusion grain boundary is more severe and the different damage of the source/drain junction in the TFT with grain boundary closed to source side. We also try to change the voltage waveform that will be divided into four parts; rising time, T Vg_high, falling time and the T Vg_low; and to investigate that how the ac stress waveform influences the degradation of the poly Si TFTs. The device degradation is strongly dependent on the falling time (Tf ) and the time at low level (T Vg_low).