寬頻矽基板覆晶片結構及低功率基底趨動混頻器之設計

Abstract

本篇論文提出一個適用於毫微米波頻段之無凸塊覆晶片結構，以及高效能、低功率射頻積體電路之設計。 本論文所提之覆晶片技術，利用金金熱壓合技巧，使得覆晶片結構能夠提供從晶片上之微帶線到戴具上之共平面帶線之間連續的特徵阻抗及平順的電流流動。參數最佳化顯示，此覆晶片結構之結構參數對於頻率響應並不敏感。量測結果顯示，頻率到50GHz之前，具有1.7dB的插入損耗，及15dB的返迴損耗。此覆晶片結構具有寬頻的特性，並且不需要額外的匹配網路。 電壓控制振盪器之設計，乃利用該覆晶片技術，整合微機電之高品質因素電感，及CMOS晶片，分別設計二個操作於5GHz之電壓控制振盪器，以達成低功率，高效能的目的。其中一個電壓控制振盪器，設計為具有高的優劣評比，在功率消耗僅1.03mW情況下，其優劣評比為191.2dB，頻率調整範圍為7.9%；另一個電壓控制振盪器，設計為具有寬的頻率調整範圍，在功率消耗僅為1.08mW情況下，其頻率調整範圍為20.2%，優劣評比為188dB。操作電壓皆為1V。 混頻器之設計，應用於無線近身網路，乃利用LO基底趨動之電路架構，結合切換級及轉導級於單一顆電晶體，以達成低電壓，電功率之目的。並且利用變形之Volterra級數進行基底趨動混頻器之最佳化設計，發現電壓轉換增益和三階互調乘積的本質來源分別源自於二階和四階非線性電流。量測結果顯示，當基底趨動混頻器操作於1.4 GHz及1V之操作電壓下，具有16dB的電壓轉換增益，-0.5dBm的第三階交會點，18.1dB的返迴損耗，及19.65dB的雜訊指數，其等待功率消耗為0.25mW，操作功率消耗為0.69mW。

This thesis proposes designs of a bump-less flip-chip structure applicable to millimeter-wave frequency, and radio frequency (RF) integrated circuit with low power and high performance. The proposed flip-chip structure using Au-Au thermo-compression technique to make the flip-chip structure provides continuity of characteristic impedance from the on-carrier CPW line to the on-chip microstrip line, as well as smooth current flow. Parameter optimization further indicates that the structural parameters in transition are insensitive to the frequency response. Measurement results show that return loss is better than 15dB and insertion loss smaller than 1.7dB up to 50GHz. The transition structure has broadband performance without any external matching network. Flip-chip technique is employed to integrate with high-quality (Q) MEMS inductor and CMOS chip to design two VCOs operating in 5 GHz for the purpose of high performance and low power consumption. One of the two VCOs is designed with high figure-of-merit (FOM). Under power consumption of 1.03mW, the VCO has FOM of 191.2dB and tuning range of 7.9 %. The other is designed in wide tuning range. The VCO has tuning range of 20.2% and FOM of 188dB consuming only 1.08mW. The supply voltage is 1V in these two VCOs. As for mixer design at the application of wireless body area network (WBAN), a bulk-driven architecture is adopted to merge switching stage and transconductance stage into a single transistor for the objectives of low voltage and low power operation. Variant Volterra series is also used for the optimization of bulk-driven mixer. The insight of nonlinear operation of bulk-driven mixer is gained that the intrinsic conversion gain and the third-order inter-modulation product (IM3) originate from the second-order and fourth-order nonlinear currents, respectively. The bulk-driven mixer operates in 1.4 GHz under supply voltage of 1V. The measurement results show that the voltage conversion gain is 16dB, the input return loss is 18.1dB, the IIP3 is -0.5dBm, and the NF (DSB) is 19.65dB. The power consumption is 0.25mW in standby mode and 0.69mW in operating mode.