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dc.contributor.author余明爵 en_US
dc.contributor.authorMing-Jiue Yuen_US
dc.contributor.author雷添福en_US
dc.contributor.authorTan-Fu Leien_US
dc.date.accessioned2014-12-12T03:02:20Z-
dc.date.available2014-12-12T03:02:20Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009411521en_US
dc.identifier.urihttp://hdl.handle.net/11536/80433-
dc.description.abstract在本論文的第二章中,我們討論金屬閘極的功函數在經過不同溫度的退火處理所產生的變化。我們利用一組有系統的數學算式來萃取準確的金屬閘極功函數。我們期望在記憶體抹除操作時,金屬閘極的功函數可以在減少經由阻障介電質的EBT (eliminating electron back tunneling)現象中扮演重要的角色。 在本論文的第三章中,我們提出金屬閘極的功函數對於高介電係數二氧化鈰奈米微晶粒作為記憶體元件的電荷捕捉層的衝擊。我們利用不同的閘極材料應用在高介電係數二氧化鈰奈米微晶粒作為電荷捕捉層的記憶體元件上,來探討元件抹除效率的提升。 在本論文的第四章中,我們提出一個利用高介電係數二氧化鈰奈米微晶粒作為電荷捕捉層的高效能非揮發性記憶體。在資料保存期間的嚴重漏電流問題,可以藉由奈米微晶粒的元件結構有效減少。因為奈米微晶粒在穿隧氧化層中彼此分離,因此存在奈米微晶粒中的電子不會一條漏電路徑就全部漏光。因此奈米微晶粒元件結構的穿隧氧化層厚度可以繼續微縮,來達到更快的寫入速度和更低的操作偏壓。另外我們改變不同的源極汲極離子佈植來達到更優越的記憶體特性。zh_TW
dc.description.abstractIn chapter 2,we discuss the dependence of metal gate work functions on the different annealing temperatures. we found a systematic methodology to extract the accurate work function of metal gates .We expect metal gate work-function can play a key role in eliminating electron back tunneling (EBT) through the blocking dielectric during the erase operation. In chapter 3,we have carry out a study on the impact of metal gate work function on the memory properties of high-k CeO2 nanocrystal based CTF memories. Schemes to improve erase efficiency of high-k CeO2 nanocrystal CTF memory devices with different metal gates are discussed. In chapter 4,we purpose a high performance nonvolatile memory with high-k CeO2 nanocrystal charge trapping layer. The serious leakage problem during retention can be eliminated by utilizing a nanocrystal memory structure. The electrons stored on the nanocrystal directly above the defect chain will be affected since the nanocrystals are separated from each other within the gate oxide dielectric. The tunnel oxide thickness in the nanocrystal memory device can be reduced to allow faster programming and lower voltage operation. We also use different source/drain implantation approaches to achieve superior memory characteristics.en_US
dc.language.isoen_USen_US
dc.subject元件zh_TW
dc.subject記憶體zh_TW
dc.subject奈米微晶粒zh_TW
dc.subject高介電zh_TW
dc.subject金屬閘極zh_TW
dc.subject離子佈植zh_TW
dc.subjectdeviceen_US
dc.subjectmemoryen_US
dc.subjectnanocrystalen_US
dc.subjecthigh-ken_US
dc.subjectmetal gateen_US
dc.subjectimplantationen_US
dc.title應用不同金屬閘極和源極汲極離子佈植於二氧化鈰奈米微晶粒之SONOS記憶體研究zh_TW
dc.titleThe Study of High-K CeO2 Nanocrystal Flash Memory with Different Metal Gates and Source/Drain Implantationsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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