標題: 高功率氮化鎵異質結構場效電晶體之設計與製作
Design and Fabrication of AlGaN/GaN Heterostructure Field Effect Transistors
作者: 王勇智
Yung-Chih Wang
林聖迪
Sheng-Di Lin
電子研究所
關鍵字: 氮化鎵;異質結構場效電晶體;高電子遷移率電晶體;高功率;高崩潰電壓;場效電板;GaN;Heterostructure Filed Effect Transistors;HEMT;high power;high breakdown voltage;field plate
公開日期: 2006
摘要: 本論文中我們研究氮化鎵異質結構場效電晶體,以達到元件高崩潰電壓的目的。我們設計了三種不同幾何結構分別為:線形結構、環形結構以及矩形結構的元件,從當中分析不同幾何結構對於元件特性的影響。同時我們設計了場效電板搭配這三種不同幾何結構以期待得到更佳的耐壓表現。我們成功地製作出線形、環形和矩形三種不同的氮化鎵異質結構場效電晶體,量測其直流、崩潰電壓與元件切換特性,並進一步觀察不同幾何結構對於元件特性的影響。實驗中線形結構、環形結構、矩形結構的崩潰電壓分別可達200V、270、350V以上。除此較高的崩潰電壓表現外,封閉式結構還可以有效地降低current collapse與gate lag的影響。封閉式結構較優越的元件特性主要有兩個原因。一:封閉式結構的閘極只會有一處跨過主動區邊緣。二:封閉式結構不像傳統線形結構在閘極末端處有尖端大電場的存在,於是有更加均勻的電場分佈。因此,比起傳統線形結構,封閉式結構的設計成功地改善了元件的崩潰電壓並且減緩了current collapse與gate lag對元件的影響。
In this thesis, the AlGaN/GaN heterostructure field effect transistors were investigated to achieve high breakdown voltage. Three types of geometry layout: line, ring and square gates, were designed and analyzed. The field-plate design was also used in the three kinds of device layouts to improve the device performance at high voltages. We have successfully fabricated the AlGaN/GaN HEMTs with line, ring, and square gates. Their DC, breakdown and switch characteristics were measured to study the influence of the different geometry layout on device performance. For the devices with line, ring and square gates, the breakdown voltages were higher than 200V, 270V and 350V, respectively. The devices with closed gates also showed much smaller current collapse and gate lag effects. The superior performances of the closed gate devices mainly come from two reasons. First, there is only one overlapped area between the gate finger and the mesa edge in closed gate devices. Second, unlike the traditional line gate device having higher electric field around the sharp tips of gate finger, the closed gate one has more uniform distribution of electric field. As a result, comparing with the conventional line gate structures, the closed gate structure successfully improved the breakdown voltage and eased current collapse and gate lag effects.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411560
http://hdl.handle.net/11536/80474
Appears in Collections:Thesis


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