利用氟摻雜前處理技術應用於高介電常數閘極介電層薄膜電晶體之研究

Abstract

在本論文中，首先，我們在成長複晶矽薄膜電晶體通道之後，運用氟離子佈值在複晶矽通道上，再整合氮化鈦金屬閘極與高介電常數材料三氧化二鐠，以形成低溫複晶矽薄膜電晶體(poly-Si TFTs)。使用三氧化二鐠可達到比目前常見的高介電常數材料還要高的介電常數，且其還有較低的閘極漏電流和卓越的熱穩定性。利用氮化鈦金屬閘極取代傳統複晶矽閘極可降低閘極片電阻。此外，氟離子佈值會鈍化捕陷狀態與消除應力鍵結去產生較強的氟鍵結，進而改善元件的特性。與未離子佈值的複晶矽薄膜電晶體比較之下，適量的離子佈值過後的複晶矽薄膜電晶體可提高導通電流，降低閘極漏電流，與改善可靠度。 另外，取代氟離子佈值，我們導入新穎的技術。即，在成長複晶矽薄膜電晶體通道之後，使用電漿增強化學蒸鍍系統(PECVD)在通道表面上打四氟化碳電漿(CF4 plasma)，再結合氮化鈦金屬閘極與三氧化二鐠，形成低溫複晶矽薄膜電晶體(poly-Si TFTs)。同理，與未打四氟化碳電漿的傳統複晶矽薄膜電晶體做比較，有打四氟化碳電漿的複晶矽薄膜電晶體擁有較高的導通電流，較低的閘極漏電流與閘極引發汲極漏電(GIDL)，並且改善次臨限擺幅(Subthreshold Swing)與可靠度的提升等等。然而過強的四氟化碳電漿會造成電漿傷害，進而造成元件劣化。 最後，我們分別對電漿處理與氟離子佈值過後的複晶矽薄膜電晶體進行熱載子應力測試之研究。實驗結果顯示，有經過電漿處理與氟離子佈值過後的複晶矽薄膜電晶體，其可靠度有明顯改善，這是由於氟會取代在複晶矽通道之中和矽與二氧化矽的界面處，較弱的矽氫鍵結，去形成較強的矽氟鍵結，進而提高對應力的免疫力。

In this thesis, first, after being deposited the poly-Si channel of the thin-film transistors, we use fluorine ion implantation on the poly-Si channel incorporated with TiN metal gate and high-□ praseodymium oxide (Pr2O3) material to obtain low temperature poly-silicon TFTs. The dielectric constant value of high-□ Pr2O3 material is higher than the common high-□ materials and the poly-Si TFT with Pr2O3 gate dielectric exhibits lower gate leakage current and perform the superior thermal stability. Instead of conventional poly-silicon gate electrode, TiN metal gate can decrease the gate sheet resistance. In addition, fluorine ion implantation can passivate the trap state and relax the strain bonds to form stronger fluorine bonds, and then improve the performance of thin-film transistors. Comparing with no ion-implanted poly-Si TFTs, the poly-Si TFTs with appropriate dosage of ion implantation can raise the driving current, decrease the gate leakage current, and improve the reliability. Besides, instead of fluorine ion implantation, the novel technique was introduced and the processing fabrication is as follows, after being deposited poly-Si channel, utilizing CF4 plasma treatment on the poly-Si surface of the channel in the plasma-enhanced chemical vapor deposition (PECVE) and incorporating with TiN metal gate electrode and Pr2O3 gate dielectric obtain the low temperature poly-silicon thin film transistors. The mechanism for the improvement of performance is the same as fluorine ion implantation, and the poly-Si TFTs with CF4 plasma treatment own the higher driving current, lower gate leakage current and gate-induced-leakage current (GIDL), improve the subthreshold swing, and raise the reliability compared to the poly-Si TFTs without CF4 plasma treatment. However, the excess RF power of CF4 plasma treatment would cause plasma damage, and then create the degradation of device. Finally, we examine the treated poly-Si TFTs on the hot-carrier stress test. Experimental results have shown that the poly-Si TFTs with CF4 plasma and fluorine ion-implanted treatment would improve the reliability. This is due to fluorine pile-up in the interface between poly-Si channel and gate dielectric, and it can be in place of the weak Si-H bonds to form a strong Si-F bond. Thereby, it can raise the immunity against the hot carrier stress.