二氧化鉿與氧化鋁鉿之堆疊式閘極在金氧半場效電晶體上的特性研究

Abstract

隨著金氧半場效電晶體尺寸的微縮，傳統的閘極介電質-二氧化矽-厚度微縮到1到1.5奈米時，大量的漏電流將會從介電層直接穿遂過去，嚴重傷害到電晶體的可靠度與特性，因此利用高介電常數介電質來取代傳統的二氧化矽是勢在必行的。因為高介電常數介電質在與二氧化矽相等的等效厚度下，有較厚的實際介電層，故可以抵擋大量的直接穿遂電流。然而，在高介電常數的介電質中所產生的遷移率衰減與臨界電壓的不穩定都是其主要的存在問題。所以提昇驅動電流大小並且了解高電藉常數介電質導致的可靠度下降問題都是本研究主要的探討重點。 本論文首先探討氧化鋁鉿應用在堆疊式閘極N型金氧半場效電晶體下的特性。經由電壓-電流與電壓-電容等圖來萃取此高介常數介電質的等效厚度。另一部分，實驗中使用電漿增強式化學氣相沉積之氮化矽層，沉積在二氧化鉿與氧化鋁鉿的金氧半場效電晶體上，利用較厚的氮化矽厚度會產生較大的伸張應力現象發現N型金氧半場效電晶體之驅動電流隨著氮化矽厚度增加而增大。接著，我們也探討，二氧化鉿高介電常數介電質材料具伸張應變通道的金氧半場效電晶體，其定電壓應力的可靠度特性分析以及偏壓變溫不穩定特性(BTI)。發現雖然較厚的氮化矽厚度可以提升N型金氧半場效電晶體的驅動電流，但定電壓應力、偏壓變溫不穩定特性卻在覆蓋較厚的氮化矽之電晶體下更為嚴重。特別是在高溫條件下，氮化矽層造成的區域應力導致較多的介面狀態產生，這可能是由於通道內的應能量造成大量矽氫鍵結斷裂。

As the conventional SiO2-based gate insulator scales down to 1.0nm~1.5nm, a large direct tunneling current generates through ultra-thin oxide which cause a serious degradation in reliability and performance of device. Utilizing high-k dielectric to replace SiO2-based gate as an insulator to eliminate high leakage current is necessary due to its larger physical thickness under the same equivalent oxide thickness. However, mobility degradation and threshold voltage instability are the mainly concern. Therefore, enhance mobility while keeping low leakage current is our aim to realize. Beside, the reliability discussion for high-k dielectric needs to be understood. In this thesis, the electrical characteristics of HfAlO/SiON gate stack of nMOSFET is discussed first. We extract the equivalent oxide thickness of HfAlO by capacitance-voltage curve and we carried out with capping SiN layer on HfAlO/SiON and HfAlO/SiON gate stack. The SiN film deposited by PECVD is used to induce tensile strain locally in the channel region. Driving currents on nMOSFETs devices are enhanced as the thickness of SiN layer increases due to increasing tensile strain in the channel region. Constant voltage stress (CVS) and bias temperature (BTI) characteristics of nMOSFET with tensile strain in the channel region are also discussed. We can find that the nMOSFETs devices with thicken SiN capping layer enhances drive current, the reliability concerns on CVS and BTI become huger when thicken SiN capping layer deposited. More interface states are generated in high CVS of nMOSFET with thicken SiN capping layer. This expresses that a higher amount of hydrogen incorporated during SiN capping layer deposition as well as the high strain energy stored in the channel.