鎳金屬矽化物誘導橫向結晶垂直通道低溫複晶矽薄膜電晶體之研究

Abstract

摘 要 在本論文中，首先研究以金屬誘導橫向結晶方法完成水平結構的複矽晶薄膜電晶體。從文獻中發現傳統的金屬誘導結晶方式，是將鎳金屬直接鍍在所定義的通道兩端後，再去做橫向誘導，使得通道兩端造成金屬污染，因此我們將鎳金屬鍍在遠離通道處，以完成金屬誘導。由結果推論由於在沉積非晶矽閘極時，先前非晶矽通道部分，已部分轉變成複晶矽薄膜通道，導致金屬誘導結晶時，電子遷移率並沒有顯著的增加，但次臨界特性以及漏電有明顯的改善，因此，在第二個部分，將改變結構，用後沉積非晶矽通道的底部閘極薄膜電晶體為主體，以保持通道部分必為非晶矽薄膜，去做鎳金屬橫向誘導的研究。 有關垂直通道結構的複晶矽薄膜電晶體，以底部閘極結構的薄膜電晶體為構想，垂直通道的長度部分主要是由閘極高度所控制並不受限於微影技術的限制，因此能以限有的微影機器，做出原本微影限制之下的線寬，而源極和汲極定義的位置與原本頂部閘極結構的複晶矽薄膜電晶體一樣，是在閘極的兩端，因此在離子佈值時，除了源極和汲極兩端之外，在閘極氧化物的頂部的複晶矽薄膜也是有摻雜雜質的區域，此區域在傳統的底部閘極結構原本是通道區域，是由於本研究的汲極源極定義位置，加上垂直通道是在閘極的左右兩側,因此造成此區域,在後續的研究也會探討到這個區域是否對電性造成影響，而在此結構的電極安排使得等效於一個雙閘極的電晶體結構，希望能增加閘極的控制能力，減少短通道效應的發生。 接著，是延續垂直通道的研究，希望能有效的提升電子遷移率，因此以鎳金屬誘導橫向結晶的方式使通道形成較大的結晶，減少矽晶粒之間的缺陷，而在初步的研究，發現以鎳金屬直接誘導橫向結晶的方式，經由低溫長時間回火之後，由於鎳金屬擴散的關係，完成誘導結晶之後，有過多的鎳金屬聚集在頂部參雜的中間區域，而造成過多的缺陷累積，雖然電子遷移率有效的提升，但整體的電性並不如預期，因此提出先形成鎳金屬矽化物後，將未反應的鎳金屬或金屬氧化物去除之後，再進行鎳金屬矽化物誘導橫向結晶處理，經由結果觀察得知在頂部摻雜區域部分沒有明顯的鎳金屬累積或污染，並且得到很好的整體電性，除了電子遷移率有效提升之外，次臨界特性以及導通電流都能有效改善。

ABSTRACT

In this thesis, we first study about horizontal channel poly crystalline thin film transistors by metal induced lateral crystallization (MILC). It is known that nickel deposition on source and drain regions cause metal contaminations on these regions after the MILC process. Thus we use nickel deposition on offset regions of metal to complete the MILC process. Because the result of the experiment shows that the field effective mobility has no remote effect after the MILC process even though the sub-threshold swing and leakage are reduced effectively, we infer that the a-Si channel film has be transferred to poly-Si during the deposit of a-Si gate rather than the MILC process. Thus in the next part of the thesis, the device structure is changed: the structure would be based on button gate thin film transistors, which would keep a-Si channel due to it is deposited after poly Si gate. With the vertical channel poly crystalline thin film transistors, the idea based on button gate structure thin film transistors, the vertical channel length is defined by gate electrode height rather than lithography technology. We can then fabricate this device, which has shorter channel size by lithography machine (G-Line stepper), and the source/drain regions is the same as the traditional top gate thin film transistors defined at both sides of the gate. When the source/drain implants, the floating N+(P+) region is formed on the gate electrode because of the design positions of source, drain and channel regions. We will further discuss the influence of this floating region as well as how this vertical structure is equivalent the dual gate thin film transistor due to the arrangement of electrodes. We hope that it can induce the gate’s controllability and reduce the short channel effect The study of vertical channel with high field effect mobility by Ni induced lateral crystallization, which can form larger grains on channel regions and reduce grain boundary defects. We detect the method of Ni induced lateral crystallization through high field effective mobility, but that accumulates too much Ni on floating N+ (P+) region and causes defects and metal contamination. As Ni is used to form silicde and then proceed to low temperature annealing, we can observe the floating region that has no Ni acumination regions or contaminations. This aids us in obtaining good electronic performance of this device, not only the remote field effective mobility but also the vast improvement of sub-threshold swing and on/off currents.