高速低密度同位元檢查碼解碼器於IEEE 802.3an之設計與實作

Abstract

這篇論文實作一個用於IEEE 802.3an標準的 (2048, 1723) 低密度同位元檢查碼解碼器。根據IEEE 802.3an標準中採用的低密度同位元檢查碼的結構，在選擇訊息儲存位址時，我們提出使用移位暫存器代替多功器的架構，可減少硬體的使用量與繞線的複雜度。同時採用部份平行化的架構不僅讓面積縮小，也減少繞線困難性。在表現出相同的位元錯誤率的條件下，使用階層解碼演算法可以有效降低解碼迴圈數。使用UMC 90nm製程實作後，在操作頻率100MHz時所提出的架構可以達到最高傳輸速率每秒5.6G bits。實作後完整的低密度同位元檢查碼解碼器核心面積大小是4.0 x 4.0 mm^2，在電壓供應0.9伏特的平均功率消耗為993mW。

In this thesis, a (2048, 1723) LDPC decoder applied to IEEE 802.3an standard is implemented. According to the structure of the LDPC code adopted in IEEE 802.3an, the architecture using shift registers instead of multiplexers for message storage is proposed to reduce the hardware cost and routing congestion. The partial parallel scheme is used for decreasing area as well as routing resource. The layered decoding algorithm is also applied for decreasing decoding iterations with similar BER performance. After implemented with UMC CMOS 90nm process, the proposed decoder can achieve 5.6 Gbps decoding throughput under clock frequency of 100MHz. The core size is 4.0 x 4.0 mm^2 and the average power consumption with a 0.9V supply is 993mW.