H.264編碼器及其可調適延伸版解碼器之加速和TI DSP系統平台之實現

Abstract

隨著數位訊號處理的進步，及時的視訊傳輸已成為生活必需的ㄧ部份。本篇論文主要是利用數位訊號處理器去實現基本的H.264/AVC解碼器以及H.264/AVC可調適延伸版的解碼器，此數位訊號處理器環境為Sundance的SMT395型號，其上核心為德州儀器公司TMS320C6416T，是個擁有強大的數學運算功能處理器。 在程式執行方面，針對H.264/AVC編碼器，是以公開軟體x264為基礎來移植於數位處理器平台，另外 Mode decision為主要加速的部份，我們使用一些判斷式減少一些不需要的Mode的計算量，這樣可以節省13%的編碼時間，在DSP實現方面，我們使用TI DSP 編譯器所提供的各種最佳化的相關工具來加速，並支援2層Cache的模式，這樣可以達到19倍左右的加速，另外針對DSP的架構使用了一些程式技巧，包括定點式資料型態、記憶體規劃、TI DSP 所支援的特殊指令群等等，可以減少50%的運算量，以QCIF的圖形，在某些畫面下，最後可以達到每秒編碼40張左右的速度。 針對延伸式H.264/AVC解碼器部份，主要是使用參考軟體 JSVM 5.0做修改，延伸式H.264/AVC主要分為Temporal、Spatial、SNR等3種不同型態的可調適，在DSP實現方面，我們先針對3種不同可調適環境做分析，在三種型態合併的情況下，針對最耗費計算量部份做加速，主要為FGS和Inter-layer Prediction這2部分，在FGS部分，做程式的修正，避免不必要的計算，在Inter-layer Prediction部分主要是減少Intra和Residual的計算量，配合DSP所提供的ㄧ些最佳化方法，在合併的情況下，可以減少49%的計算量。

With the advancement of the digital signal processing, real-time video transmission becomes an essential element in our daily life. In this thesis, we implement the H.264/AVC encoder and the scalable extension of H.264/AVC (H.264/AVC SVC) decoder by using a digital signal processor (DSP). The digital signal processing environment is Sundance module SMT395. The core of the DSP is the Texas Instrument’s TMS320C6416T which is a powerful signal processor with strong arithmetic operation capability. For the H.264/AVC encoder, the open source code x264 is used as the basis to build a DSP-executable program. The mode decision module is the key element being accelerated. We develop an early termination method to reduce the calculation of the dispensable modes. This saves up to 13% of the encoding time. For the DSP implementation, we start with the optimization tools provided by the TI DSP complier. We also make use of the two-level cache module on the DSP platform. This can speed-up the system by about 19 times. Furthermore, we use several DSP codes acceleration techniques including fixed-point data types, TI DSP intrinsic functions and others. Through the code modifications, we can reduce the computation by 50%. Finally, the overall system can encode up to 40 QCIF frames per second on test video sequences. For the H.264/AVC SVC decoder, we start with the MPEG reference software JSVM 5.0. The H.264/AVC SVC includes three types of scalability, namely, Temporal, Spatial and SNR scalability. For the DSP implementation, we accelerate the parts which take the most computing time in the combined scalability. These two parts are the FGS and the inter-layer prediction modules. For FGS, we refine the codes to reduce the computation redundancy. For the inter-layer prediction, we reduce the up-sampling operations for the intra texture and the residuals. In addition, we also use the acceleration techniques supported by the TI DSP. The final H.264/AVC SVC decoder can reduce the computation by 49% in the combined scalability.