90奈米混合臨界電壓標準元件庫

Abstract

隨著製程的進步以及各種攜帶型電子產品需求的增加，功率消耗對於這些產品變得相當的重要，例如：使用太陽能電池的助聽器 、新型手機…等。在本篇論文中，我們提出首先介紹關於深次微米CMOS標準元件庫的時脈效能和能量特性化流程的概論。接著我們提出一種在電路中使用混合臨界電壓電晶體的方式來取代單一臨界電壓電晶體的方式，使電路能夠在不犧牲速度的情況下，達到低功率的效果。我們找出在拉升及拉降結構中延遲時間的關鍵路徑，以及關鍵路徑中最長延遲時間的關鍵電晶體。接著我們將關鍵電晶體置換成較低臨界電壓的電晶體，並且重新調整較低臨界電壓的電晶體尺寸，使新電路的速度能與原本的電路接近。利用這種方式，我們不需要增加額外的電路，也不需要更改電路架構，即可達到低功率的需求。此外大部分電晶體路徑中的漏電流將會被阻擋住。 我們利用這種混合臨界電壓的方式來建立90奈米低功率標準元件庫。接著利用這個低功率標準元件庫來合成電路並且和高臨界電壓標準元件庫的效能比較。我們的混合臨界電壓標準元件庫在動態功率消耗上可以節省5％到30％，在延遲時間功率乘積上可以節省20%到55%，而在面積方面因為佈局規則的限制，增加了0%到40%。

With the advance of process technology and the increasing requirement of portable electric products, the power consumption of these products becomes very important. In this thesis, we first make the overview about the advanced characterization flow of timing and power in deep submicron CMOS standard cell library. Then, we propose a methodology using mixed-threshold voltage transistors in a circuit instead of single normal-threshold voltage transistors to reduce power consumption with the same timing performance. We find out the critical path and the critical transistors on the critical path that result in the longest delay time in the pull-up and pull-down networks, respectively. Then we replace the critical transistors with lower threshold voltage transistors and do resizing to meet the time performance of original circuits. Using this technique, we do not have to use additional transistors and do not change the structure of circuits to obtain the requirement of low power. Moreover, the leakage current is also blocked in most of the transistor paths. We apply this mixed-threshold voltage methodology to establish our 90nm low power standard cell library. Then we use many design examples to compare the performance with the high-Vt standard cell library and make the conclusion that we can have around 5% to 30% dynamic power saving, 20% to 55% delay-power product saving and the area is 0% to 40% larger than the standard cells with single high-Vt transistors.