以低狀態機率切換與可調變擷取長度為基礎之維特比解碼器

Abstract

無線與可攜式裝置在近年來成為越來越普遍的應用。因此，低功率電路的設計已經成為一項重要考量。本論文提出一個結合低狀態切換機率與可調變擷取長度技術的維特比解碼器。在高訊雜比的環境下，低狀態切換機率技術可大幅降低解碼時的狀態切換率。基於維特比演算法的路徑融合特性，可調變擷取長度技術可消除殘餘記憶體中不必要的資料搬移。模擬結果顯示，在位元訊雜比大於4分貝的環境下，本研究所提出的方法只需13%的額外硬體，即可省下超過14%的解碼器功率消耗與53%的殘餘記憶體功率消耗。

As wireless and portable devices become more and more popular these years, low-power design has become an important issue. In this thesis, we propose a low-power Viterbi decoder combining scarce state transition and variable truncation length schemes. The SST technique reduces the state transition activity significantly in high SNR conditions. The variable truncation scheme eliminates unnecessary data movement of the survivor memory based on path merging property of Viterbi algorithm. According to the simulation results, more than 14% decoder power and 53% survivor memory power can be reduced as Eb/N0 is large than 4dB, while the overhead of 13% gate count is required.