射頻功率放大器之靜電放電防護設計

Abstract

本篇論文主旨在於設計適用於射頻功率放大器之靜電放電防護電路。其原理為利用元件或電路特性，使靜電放電防護電路對原電路的負面影響降到最低，且具有高水準之靜電放電防護能力。本論文提出兩個適用於射頻功率放大器的靜電放電防護策略，共下線了兩顆晶片以作驗證。所下線之兩顆晶片皆以標準零點一三微米互補式金氧半場效電晶體製程所製造。 第一種射頻功率放大器的靜電放電防護策略是利用電感性元件作為靜電放電箝制元件。因為靜電放電事件屬於較低頻行為，而射頻訊號佔據高頻頻譜，因此電感性元件可區分靜電放電事件和射頻訊號，作為一低阻抗之靜電放電路徑。此電感性箝制元件亦可作為輸出阻抗匹配網路之一部份，並與輸出阻抗匹配網路共同設計，因此電感性箝制元件可以對原射頻功率放大器完全無任何負面影響。同時，一個MIM電容可以與輸出訊號路徑串連，阻擋靜電放電電流直接貫穿而轟擊到內部主動核心元件，提高保護效果。實驗證明此靜電放電防護策略可有效提供防護等級超過八千伏特人體放電模式靜電放電轟擊測試，與四百伏特機器放電模式靜電放電轟擊測試。 第二種射頻功率放大器的靜電放電防護策略是利用低寄生電容之電容性靜電放電箝制元件。格狀陣列形式的矽控整流器和二極體可在相同晶片佈局面積下提供最大靜電放電路徑周長，因此可在貢獻最小寄生電容之前提下，提供最高靜電放電防護等級。實驗證明此靜電放電防護策略可有效提供防護等級超過八千伏特人體放電模式靜電放電轟擊測試，與八百伏特機器放電模式靜電放電轟擊測試。 實驗結果亦證明，靜電放電轟擊確實對射頻功率放大器的射頻操作效能有極大影響。射頻功率放大器極需靜電放電防護設計，否則無法於靜電放電轟擊存活。

The aim of this thesis is to design the ESD protection circuits which are suitable in radio-frequency (RF) power amplifiers (PA). The ESD protection capability and the influence on the performance of the RF PA circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes two RF PA ESD protection strategies which have been verified through two individual chips fabricated in standard 0.13-μm CMOS process. The first RF PA ESD protection strategy is to use an inductive ESD clamp which can be co-designed with the RF PA output matching network. An inductive device can distinguish ESD event which occupies the lower frequency spectrum from the normal RF signals. It acts as the low impedance discharging path for ESD current and provides specific impedance for RF signal. A MIMCAP in series of the signal line can block out the ESD current from directly penetrating into the active devices in RF PA core. The measurement results have verified this ESD protection strategy and proved that the proposed ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 400V MM ESD level. The second RF PA ESD protection strategy is to use capacitive ESD devices with low parasitic capacitances. Waffle-structured SCR and diodes are utilized to provide maximum discharging peripheral within a given layout area for minimizing the parasitic capacitance. The waffle-structured SCR is designed with ESD detection and trigger circuit to provide the best ESD protection capability while contributing minimal parasitic capacitance to the RF PA. The measurement results have verified the effectiveness of the proposed ESD protection strategy and proved that this ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 800V MM ESD level. Further, the measurement results also verify that an unprotected RF PA can not survive any single ESD zapping. RF PA circuitry is in urgent need of ESD protection with low parasitic effect.