具高介電常數閘極絕緣層的低溫多晶矽薄膜電晶體之研究

Abstract

在本論文中，我們詳細地探討高性能之具二氧化鉿（HfO2）的低溫薄膜電晶體之元件特性。本論文首先特別針二氧化鉿（HfO2）與多晶矽薄膜之間所產生的介面層（interfacial layer），對於低溫多晶矽薄膜電晶體的特性影響上作了仔細的分析，特別是二氧化鉿的介面層對於N型與P型通道之低溫薄膜電晶體的影響。此外，為了更進一步研究與加強二氧化鉿之低溫薄膜電晶體的特性，氧氣電漿表面處理也被使用來改善多晶矽通道的表面品質與鈍化缺陷，可增加載子遷移率與降低表面粗糙散射（surface roughness scattering）。另外，氮氣和氨氣電漿表面處理可個別地明顯地增加二氧化鉿之低溫薄膜電晶體的載子遷移率約74.4和108.5個百分比。而且，氮氣和氨氣電漿表面處理也可降低表面粗糙散射來增加在高的閘極偏壓下之載子遷移率，可個別地提升二氧化鉿之低溫薄膜電晶體的驅動電流約217和219.6個百分比。 另外，我們也詳細地探討高性能之具二氧化鉿（HfO2）的低溫薄膜電晶體之可靠度機制。施加多種偏壓與溫度的應力條件以用於釐清陷阱密度能態（trap density states）的分佈與機制。藉由施予閘極正偏壓應力（PBS）與閘極正偏壓高溫應力（PBTI）在二氧化鉿之低溫薄膜電晶體上，可以觀察到等效介面層之深層陷井能態的產生、多晶矽晶界之淺層陷井能態的產生、以及二氧化鉿之電子捕捉。而閘極負偏壓應力（NBS）與閘極負偏壓高溫應力（NBTI）施予在二氧化鉿之低溫薄膜電晶體可以觀察到等效介面層之深層與淺層陷井能態的產生。 除了電漿表面處理之外，氟與氮離子佈植法配以固態低溫活化法也可達到高性能的二氧化鉿之低溫薄膜電晶體。對於氟離子佈植法而言，二次離子質譜儀的分析展現了與過往研究中不同的氟離子分佈，造成約有百分之25的晶界缺陷陷阱被氟離子鈍化且導致漏電電流降低約十倍。另外，熱載子效應對於臨界電壓不穩定度也有了改善。具二氧化鉿之低溫多晶矽薄膜電晶體配以氟離子佈植法可達到低臨界電壓約1.32 V、優異的次臨界斜率約0.141 V/decade、和高開關電流比1.98 x 107。然而對於氮離子佈植法而言，二次離子質譜儀的分析展現了氮離子在佈植後的退火過程中，將會聚集在多晶矽通道與絕緣層的介面處，對於N型低溫多晶矽薄膜電晶體而言，將會造成百分之54.9的驅動電流增加量，然而對於P型低溫多晶矽薄膜電晶體而言，將會造成百分之16.7的驅動電流增加量。因此，對具二氧化鉿之低溫多晶矽薄膜電晶體配以氮離子佈植法可達到低臨界電壓：N型約為1.05 V，P型約為-0.8 V、優異的次臨界斜率：N型為0.213 V/decade，P型為0.123 V/decade、以及較高的載子遷移率：N型為37.80 cm2/V-s，P型為64.14 cm2/V-s。這些具二氧化鉿之低溫多晶矽薄膜電晶體的改善，均歸功於較高的閘極電容密度以及氟與氮離子對於多晶矽薄膜缺陷的鈍化。 最後，此論文也展示了利用金屬側向誘發結晶法配以氮化鉭/二氧化鉿（TaN/HfO2）結構之P型通道低溫薄膜電晶體。低臨界電壓約0.095 V、優異次臨界斜率約83 mV/decade、和超高載子遷移率240 cm2/V-s可被實現而不需要任何的缺陷鈍化處理。此明顯的電性改善主要是來自於利用金屬側向誘發結晶法所產生的通道薄膜以及非常高的閘極電容密度。

In this dissertation, the impacts of HfO2 interfacial layer on n- and p-channel LTPS-TFTs are specified. In order to enhance the characteristics of HfO2 LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, resulting in increasing the carrier mobility and reducing the surface roughness scattering. Moreover, significant field effect mobility □FE improvement ~ 74.4 % and 108.5 % are observed for LTPS-TFTs with HfO2 gate dielectric after N2 and NH3 plasma surface treatments, respectively. In addition, the N2 and NH3 plasma surface treatments can also reduce the surface roughness scattering to enhance the field effect mobility □FE at high gate bias voltage VG, resulting in 217.0 % and 219.6 % improvement in driving current, respectively. In addition, a comprehensive study of the reliability mechanisms of the high performance low-temperature poly-Si thin-film transistor (LTPS-TFT) with HfO2 gate dielectric is also demonstrated. Various bias and temperature stress conditions, which correspond to positive bias stress (PBS), positive bias temperature instability (PBTI), negative bias stress (NBS), negative bias temperature stability (NBTI), and hot carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep trap states of the effective interfacial layer, tail trap states of poly-Si grain boundaries, and electrons trapping of the HfO2 gate dielectric are observed for the PBS and PBTI of the HfO2 LTPS-TFT. In addition, both the deep and tail trap states of the effective interfacial layer are generated under NBS and NBTI of the HfO2 LTPS-TFT. Moreover, In addition to the plasma surface treatment, fluorine and nitrogen ion implantation with low temperature solid-phase crystallized activation scheme is used to obtain a high performance HfO2 LTPS-TFT. For fluorine ion implantation of LTPS-TFT, the SIMS analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of Imin is achieved due to 25 % grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine pre-implantation can simultaneously achieve low VTH ~ 1.32 V, excellent S.S. ~ 0.141 V/decade, and high Ion/Imin current ratio ~ 1.98 x 107. For nitrogen ion implantation of LTPS-TFT, the SIMS analysis shows the nitrogen atoms would pile up near the surface of poly-Si channel film after SPC process. For n-channel LTPS-TFT, a ~ 54.9 % driving current IDsat improvement is found. For p-channel LTPS-TFT, a ~ 16.7 % driving current IDsat improvement is found. Finally, a high performance CMOS LTPS-TFTs with threshold voltage VTHn ~ 1.05 V, VTHp ~ –0.8 V, subthreshold swing S.S.n ~ 0.213 V/dec., S.S.p ~ 0.123 V/dec., field effect carrier mobility □nFE ~ 37.80 cm2/V-s and □pFE ~ 64.14 cm2/V-s are derived. The performance improvements of LTPS-TFTs after NII treatment are due to the defect passivation near the surface channel by nitrogen atoms. Finally, high-performance low-temperature poly-Si (LTPS) p-channel thin-film transistor (TFT) with metal-induced lateral crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated. Devices of low threshold voltage VTH ~ 0.095 V, excellent subthreshold swing S.S. ~ 83 mV/dec., and high field effect mobility □FE ~ 240 cm2/V-s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate capacitance density provided by HfO2 gate dielectric with the effective oxide thickness (EOT) of 5.12 nm.