奈米點應用於先進非揮發性記憶體之製作與特性研究

Abstract

近年來，以傳統浮閘(Floating gate)記憶體為基本元件之非揮發性固態半導體記憶體已被廣泛的應用於各種電子產品。為獲得更高密度、低功率損耗與快速讀寫的操作驅使目前非揮發性記憶體在元件尺寸上持續的微縮。然而傳統浮閘記憶體在寫入與抹除的持續操作後，會在穿遂氧化層產生漏電路徑使得原本儲存的電荷全部流失回到矽基版，而且這個情形隨著尺寸的微縮而更加的嚴重。因此，在資料保存時間(Retention)和耐操度(Endurance)的考量下，微縮穿遂氧化層的厚度是非常困難的。具非揮發性的奈米點記憶體被提出並存有希望可取代傳統浮閘記憶體。由於以空間上與電性上分離的奈米點作為儲存中心，所以可以有效改善尺寸微縮時，記憶體元件在多次讀寫操作後的資料儲存能力。除了奈米點記憶體外，電阻式非揮發性記憶體(RRAM)近年來也成為學者與工業界的焦點。主要是由於其製程簡單且與動態隨機存取記憶體(DRAM)製程相似，可以被整合到半導體的後段製程。電阻式記憶體擁有高速、非揮發性與低電壓操作的特性等優點。 在本論文中，我們將研究鉬(Mo)與鉬化矽作為奈米點材料來克服傳統非揮發性記憶體在微縮過程中會遭遇到的困難。相較於其他金屬材料，鉬具有低價格，高溫熱穩定性，與高功函數等優點。我們首先提出對鉬化矽退火以形成鉬金屬奈米點，並應用在奈米點非揮發性記憶體上。在室溫環境中，利用雙電子槍(dual electron-gun)同時以一比三的比例蒸鍍矽與鉬(Si and Mo)的方式來形成奈米點自我形成層，再以退火的方式使奈米點形成。在我們的實驗中，我們發現奈米點的大小與組成的成分會因退火的氣氛(ambience)不同而有所差異。在氮氣熱退火下，可以發現所形成的奈米點大約5-nm且所組成的成分主要為矽化鉬(MoSi2)，而在氧氣退火下，會使得所形成的奈米點大小約20-nm且組成成分以氧化鉬為主(Mo oxide)。除此之外，我們發現在氧氣退火前先疊一層氧化矽可阻擋氧化鉬揮發。此為形成氧化鉬奈米點的一個關鍵步驟。 近年來已經發展了許多方法來形成金屬奈米點記憶體，一般而言，大多數的方法都需要長時間的熱退火製程在氧氣的環境下，這個步驟會影響現階段半導體製程中的熱預算和產能且同時造成金屬奈米點過氧化的現像。因此在本論文中，我們使用一個簡單且快速的製程方法來形成金屬鉬奈米點，並將其應用於非揮發性記憶體元件上。我們在氬氣和氧氣(Ar/O2)的環境中濺鍍鉬與矽的混合層，藉由熱退火於氮氣環境下來形成奈米點。利用形成氧化物時不同形成能(formation energy)的差異，可以在氮氣快速退火的過程中形成金屬奈米點。同樣的我們也利用此方法濺鍍鉬與矽的混合層在(Ar/N2)的環境中，我們發現，高密度(6×1012 cm-2)的鉬金屬奈米點可以被形成於氮化矽(SiNx)中，這將有助於解決奈米點記憶體在元件尺寸微縮時可能造成記憶體元件參數變化的問題。最後我們製作雙層鉬奈米點記憶體結構並探討其特性。相較於單層奈米點，我們發現發現多層奈米點不僅在室溫下且在高溫下都擁有較好的電荷儲存能力和保存能力。 由於許多製作奈米點的方法，諸如離子佈植法(ion implantation)、氧化方法(oxidation)與濺鍍法(sputtering)等都可能在形成奈米點的過程中造成奈米點周遭的介電質受到損害而影響記憶體的特性。因此，我們提出氨(NH3)電漿處理技術來改善奈米點周遭介電質的品質，以應用於非揮發性奈米點記憶體。氨電漿技術被廣泛的應用於半導體工業，由於它的低溫特性，可以降低製程的熱預算。我們在鉬奈米點嵌入氧化矽與氮化矽的記憶體元件上進行氨電漿的處理，研究中發現藉由氨電漿的處理可以引入氮鍵結於奈米點周遭的介電質。這些氮鍵結可以有效的鈍化介電質中的缺陷，並改善金屬奈米點的記憶體特性。 相較於浮閘金屬奈米點非揮發性記憶體，電阻式記憶體被廣泛的研究以期能整合於後段製程。在論文中，我們研究氧化鋁的電阻式記體特性在不同退火溫度下的影響。研究中發現，傳統金屬/絕緣層/金屬 (MIM)結構之電阻式記憶體元件的特性會有很大的變化與不穩定性，這增加了元件在設計與操作上的複雜度。因此，我們提出金屬/絕緣層/奈米點/絕緣層/金屬的結構來改善電阻式記憶體的特性。實驗的結果發現，電阻式記憶體的電流不管在開啟(ON-state)或者關閉的狀態(OFF-state)會因為金屬奈米點的嵌入而穩定下來。除此之外，由關閉狀態至開啟狀態的起始電壓變化的範圍也會縮小。最後，我們將對我們的研究主題作一總結。

Floating gate composed nonvolatile memories (NVMs) have been widely application in electronic devices in recent years. Requirements of high density, low power consumption and high speed operation drive the memory device scaling down. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down without influence of retention and endurance characteristics. Nanocrystals (NCs) NVMs are one of promising candidates to substitute for conventional floating gate memory because the discrete NCs as charge storage centers instead of continuous floating gate can effectively improve data retention for the device scaling down. On the other hand, resistive switching random access memories (RRAM) have recently received academic and industry’s attention for its benefit of high density, high operation speed and simple structure. Furthermore, the fabrication process of RRAM is similar to that of DRAM, and therefore can be easily integrated into back-end process of memory device. In this thesis, we propose Mo and Mo silicide as material for fabrication of nanocrystal to overcome the limitation in conventional NVMs during the scaling down process. Compared with other materials, Mo-based material has advantages of low cost, high thermal stability and high work function. Furthermore, Mo has been proposed for the metal gate, and is compatible with the MOSFET fabrication process. Besides, for back-end memory process, we embedded nanocrystal in RRAM to reduce variation of memory characteristics of RRAM. First, we proposed a Mo silicide serving as NCs self-assembling layer for application in NCs NVMs. Mo silicide layer was deposited by dual electron-gun evaporation of Mo and Si pellets at room temperature, and a post annealing was performed to form NCs. In our results, we found that annealing ambience can influence the size, density and composition of NCs. When Mo silicide layer annealing in N2 ambience, the size of NCs is about 5-nm, and the composition of NCs is dominated by MoSi2. However, when annealing in O2 ambience, Mo oxide NCs was formed and its size is about 20-nm. In addition, we found that a pre-annealing-capping oxide layer is a key process to form Mo oxide NCs. There are many methods have been develop to form nanocrystals for nonvolatile memory application. Most of the methods need long-term annealing in oxygen ambience. This procedure will influence thermal budget and throughput for the current manufacture technology of semiconductor industries. Hence, a simple and fast fabrication technique of Mo NCs was demonstrated for NVM application in this thesis. The NVM structure of Mo NCs embedded in the SiOx layer was fabricated by annealing Mo silicate, which was deposited by sputtering Mo and Si target in Ar and O2 ambience. In the formation process, the oxygen plays a critical role for the NCs formation during sputter process. A high density (~1012 cm-2) NCs also can be simply and uniformly fabricated in our study. We also proposed a formation of Mo NCs embedded in SiNx by replacing O2 by N2 ambience during the sputtering process. A high density Mo NCs was embedded in the silicon nitride (SiNx) which presented larger memory effect. Therefore, by using internal competition mechanism in charge trapping layer for these elements (Mo, Si, and O or N), we can obtain a metallic NCs NVM with low thermal budget process. Besides, double-layer NCs NVM structure was fabricated in this work. We found that double-layer NCs structure has better charge storage and retention over than single-layer one under high temperature test because of Coulomb blockade effect can be reduce by sharing the stored carriers into both the first layer and second NCs layer. Furthermore, carriers stored in the first layer can build-up Coulomb expulsion force to reduce the tunneling probability of carriers stored in the secondary NCs layer. Many proposed methods for fabrication of NCs such as ion implantation, oxidation and sputtering are expect to induce defect in the dielectric around nanocrystals, and influence charge storage ability of memory device. Therefore, we used a post treatment of ammonia (NH3) plasma to improve the quality of the surrounding dielectric. Ammonia plasma treatment has been widely application in semiconductor industry for its low thermal budget. In this work, ammonia plasma treatment was performed on Mo NCs embedded in oxide or nitride. The results indicate that nitrogen bonding can be introduced into surrounding dielectric to passivate defects, and therefore improve the nonvolatile memory characteristics of the memory device. In addition to floating gate device, we study the resistive switching random access memories (RRAM) for application in back-end nonvolatile memories. Aluminum oxide was employed as resistive switching layer in this work. We found that the variation of resistive switching characteristics in conventional structure, metal/insulator/metal structure, is large. This increases the complexity of designing and operation of the device. Therefore, we proposed metal/ insulator/nanocrystals/ insulator/metal to reduce variation of memory characteristics in RRAM device. In the final part of this dissertation, the conclusion is presented.