以交連線為中心加強系統晶片可測試性及良率之震盪環結構與演算法

Abstract

交連線在深次微米及奈米技術中日益重要，因此，交連線的可測試性及良率之問題引起眾多學者投入研究。本博士論文是以震盪環測試結構與演算法(Oscillation Ring Architectures and Algorithms)來解決交連線的可測試性及良率之問題。我們所提出的震盪環測試機制符合IEEE1500標準並用以測試與診斷系統單晶片 (System on Chip,SoC)的交連線。 我們面對兩項技術挑戰，第一項、設計複雜度使得交連線的可測試性及良率之問題不可避免。第二項、串音雜訊使得交連線的訊號整合性及延遲錯誤之問題受到重視。 為了面對第一項設計複雜度的挑戰，我們的作法是將震盪環測試機制嵌入多接繞線器中以增進交連線的可測試性，並且提出以降低與平均繞線壅塞度的方法來增進交連線的良率之問題。 為了面對第二項交連線的訊號整合性及延遲錯誤的挑戰，我們的作法是進行一些基礎分析與研究，茲列舉如下。 (1) 為了建立交連線震盪環結構與演算法的分析架構，我們擴充早先可在交連線上加入緩衝器的研究，所以我們所提出的震盪環測試機制是可與常用的緩衝器加入技術(buffer insertion)相容。 (2) 為了測試交連線的訊號整合性及延遲錯誤，我們提出交連線串音整合偵測機制，其作法是不直接測試延遲錯誤，而是利用串音突波與串音延遲的關係來直接測試串音突波。為了證明此測試機制的有效性，我們以蒙地卡羅模擬來說明此機制即使在百分之二十的製程飄移下仍達成百分之九十二以上的測試良率。此處所發展的串音突波偵測器電路設計可用於交連線震盪環測試結構中。 (3) 為了提高交連線的可測試性，提出交連線震盪環測試結構與演算法。我們先提出基本的測試方法論，再進一步提出另一個交連線診斷與最佳化的方法與技術。 (4) 最後我們將交連線震盪環結構與演算法加以修改應用到全晶片繞線器上以及同步序向電路中。 本博士論文提出以交連線為中心加強系統晶片可測試性及良率之震盪環結構與演算法來解決交連線的可測試性及良率之問題。綜結以上各觀點，完成了五篇國際論文與提交了六篇期刊論文。

Interconnects play a dominant role in deep-submicron and nanotechnologies. As a result, testability and yield problems of interconnects attract increasing attention. The paradigm shift of the interconnect-related problems is indispensable to cope with two major challenges as technology advances into nanometer territory: □ The ever increasing design complexity of gigascale integration renders testability (detection and diagnosability) and yield enhancement inevitable. □ The complicated physical effects inherent from the scaling effects in nanoscale technology make crosstalk noise (crosstalk-induced glitch faults and crosstalk-induced delay) inevitable, and thus signal integrity and delay faults can no long be ignored. The motivation of this research is targeted at testability and yield enhancement with test time reduction at design stages by our proposed Oscillation Ring (OR) test mechanism. These advantages of the oscillation ring test mechanism have made interconnects detectable and diagnosable through a systematic graph modeling approach. As a relatively novel methodology, OR mechanism for system-level interconnects should be compliant to IEEE Std. 1500. Thus, it is desirable to consider test architectures and algorithms for interconnect testing for System on Chip (SoC) under IEEE Std. 1500, and develop interconnect-centric computer-aided-design tools including design, detection, and diagnosis. To handle the first challenge, the ever increasing design complexity of gigascale integration, we integrate our proposed oscillation ring test techniques into a signal-integrity-aware router. We propose an integrated multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) An oscillation ring test and diagnosis scheme for interconnects, based on IEEE Std. 1500, is integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework by introducing a preprocessing stage of Interconnect Oscillation Ring Detection (IORT) that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a postprocessing (final) stage of Interconnect Oscillation Ring Diagnosis (IORD) after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion, and the goals of this router include minimizing multiple-fault probability, reducing crosstalk effects, and improving yield for both chemical-mechanical-polishing (CMP) and optical-proximity-correction (OPC) induced manufacturability problems. Experimental results on the MCNC benchmark circuits demonstrate that the proposed OR method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects, and the multilevel congestion-driven routing algorithm effectively balances the routing density to achieve 100% routing completion. Experimental results show that our method significantly improves routing quality for testability and yield enhancement. To deal with the second challenge for signal integrity problem, the crosstalk-induced faults have caused significant impact on interconnect performance as technology advances into nanometer era. The crosstalk is a phenomenon of parasitic capacitance caused by continuous scaling effects. It directly influences reliability, manufacturability and yield of VLSI circuits. (1) We present buffer planning techniques for designing and analyzing crosstalk noise together with performance during floorplanning, and show theoretically and experimentally that our interconnect-aware floorplanner outperforms currently available ones with simultaneously considering crosstalk and timing as our preliminary work which paves the base for IORT and IORD. (2) There are two types of crosstalk: crosstalk-induced glitch and crosstalk-induced delay. We analyze and design the detection of crosstalk faults for interconnect bus, and show experimentally that the unified detection scheme for crosstalk-induced glitch and crosstalk-induced delay is feasible and effectively. This scheme is based on a built-in pulse detector with an adjustable threshold voltage, and we show that this design works well under process variations. Furthermore, the pulse detector in the crosstalk unified detection scheme is embedded into IEEE Std. 1500 wrapper compliant cells so that oscillation ring test for the interconnect test can handle the delay fault, which poses challenges to system performance. (3) We study interconnect detection and diagnosis problems for interconnects. We show a class of oscillation ring approximation algorithms for an interconnect detection and diagnosis problem and prove that oscillation ring mechanism with IEEE Std. 1500 compliant test architecture guarantees 100% fault detection (by IORT) and the optimal diagnosis resolution (by IORD) not only under the fault models of traditional stuck-at and open faults, but also delay and crosstalk glitch faults. Solutions to the interconnect problems by applying oscillation ring methodology pave the way for developing a novel integrated multilevel routing framework with a congestion metric for routing as mentioned above. (4) Finally, the oscillation ring test method has been successfully modified and applied to synchronous sequential circuits to facilitate at-speed test for delay fault detectable in addition to traditional stuck-at and open fault models. In summary, both testability and signal integrity issues have significant impact on interconnect design and test. In my PhD dissertation, an interconnect-centric oscillation ring architectures and algorithms targeted for SoC testability and yield enhancement is proposed to deal with system-level interconnect test and diagnosis, full-chip integrated multilevel router framework, and RTL (register transfer level) synchronous sequential circuits for at-speed testability.