十二位元超低耗能連續近似式類比數位轉換器之設計

Abstract

本論文提出利用0.18μm CMOS製程實現一12位元超低耗能連續近似式類比數位轉換器，此類比數位轉換器使用具備消除過偏移量功能的前置放大器來降低比較器的偏移量，並且使用capacitor splitting DAC來減少DAC的誤差量及功率消耗。為了得到更好訊號雜訊比值，我們使用一個具有軌對軌(Rail-to-rail)輸入範圍的放大器來作為前置放大器的第一級，使類比數位轉換器可以接受軌對軌的輸入訊號。為了讓前置放大器在低電壓下亦能正常工作，我們並聯主動式正電阻和主動式負電阻來作為其負載，使其在0.5V之下仍可正常工作。量測結果顯示，當使用供應電壓為0.55伏特且輸出頻率為1KS/s時，此連續近似式類比數位轉換器可提供軌對軌的輸入範圍，以及50.73dB的訊號對雜訊諧波比(SNDR)，且此類比數位轉換器之功率消耗只有35nW，而其有效解析度頻寬可以到達奈奎斯(Nyquist)頻寬(500Hz)，此時相對應之能源FOM (Figure of merit)可達124fJ/conversion-step，與已知文獻中功耗最低之類比數位轉換器相較，此類比數位轉換器消耗功率僅為其24分之一，為目前已知消耗功率最低的類比數位轉換器。

This paper presents a 12-bit, ultra low power successive approximation analog-to-digital converter in TSMC 0.18μm 1P6M CMOS process. The analog-to-digital converter uses the offset-free pre-amplifiers to alleviate the impacts of the comparator’s offset. The bridging capacitive DAC is adopted to reduce the nonlinearity and to save the power of the DAC. The pre-amplifiers with a rail-to-rail input range are used to make the input range of the ADC also rail-to-rail. We used a diode-connected transistor in parallel with a negative resistor as the loads of the pre-amplifers in order to enable them operating at a supply voltage as low as 0.5V. Measurement results show that at an output rate of 1KS/s and a supply voltage 0.55V, the SA ADC provides a rail-to-rail input range and achieves a signal-to-noise-distortion ratio (SNDR) of 50.7dB and an effective resolution bandwidth (ERBW) up to the Nyquist bandwidth (500Hz). Its power consumption is as low as 35 nW, corresponding to an energy figure of merit (FOM) as good as 124fJ/conversion-step. The power of the proposed ADC is 24 times better than the lowest record of the state-of-the-art works as far as we know.