離散時間單迴路積分三角類比數位轉換器之功率損耗模型建立與針對非對稱數位用戶迴路終端機應用之電路設計

Abstract

在本篇論文中，我們建立了積分三角類比數位轉換器的功率消耗模型，而我們把功率消耗模型分成類比功率消耗模型和數位功率消耗模型兩個部份，類比功率消耗模型包括積分器功率消耗模型、量化器功率消耗模型、數位類比轉換器功率消耗模型；數位功率消耗模型包括時脈產生器功率消耗模型和開關功率消耗模型。 我們針對非對稱數位用戶迴路終端機應用來做電路設計。我們選擇的電路架構為離散時間單迴路單一位元積分三角類比數位轉換器來實現非對稱數位用戶迴路終端機。

In this work, we build the power consumption model of discrete time single-loop multi-bit sigma-delta ADC, and the power consumption model of discrete time single-loop multi-bit sigma-delta ADC can be divided into two parts. The one is the analog power consumption model, and the other is the digital power consumption model. The analog power consumption model includes the integrator power consumption model, the Quantizer power consumption model and the DAC power consumption model. The digital power consumption model includes the clock driver power consumption model and the switch power consumption model. We design the circuit for ADSL-CO (central office) application. And we used the discrete time single-loop single -bit sigma-delta ADC architecture to simulate.