低功耗相位式快取記憶體之高效能管線設計

Abstract

隨著可攜式產品的應用日趨廣泛及全球能源觀念抬頭，低功率消耗成為微處理器研究中重要的一環。而快取記憶體佔了處理器一半左右的面積及功率消耗，依據Amdahl定律，如果能改善快取記憶體的功率消耗，就能帶給處理器可觀的低功率消耗的效果。快取記憶體一但失誤，需要花費大量的時間及能量跟外部記憶體存取，因此命中率嚴重影響效能及功率消耗，快取記憶體中為了提升命中率而增加的集合關聯性設計(set associative cache)，卻會造成多餘的功率消耗，因此相位式快取記憶體設計能去除不需要的集合關聯式記憶體 存取，改善這個缺失，但卻會造成雙倍存取時間的缺失，造成效能下降。 本論文針對相位式資料快取記憶體，改良處理器管線，加速讀取指令其運作，以分擔相位式快取記憶體中的Tag 存取相位，改善其耗時雙週期的缺點，去除管線暫停，只增加6%成本就達到44%低功率消耗又不增加時間負擔的設計理念。結合相位式快取及快速存取管線設計，並達到整體最高效益。為了驗證該演算法的正確性，本論文設計中結合本實驗室的嵌入式處理器，做為該資料快取記憶體的驗證平台，並整合成為一顆嵌入式低功耗處理器晶片。此晶片採用TSMC 0.18 μm 1P6M製程，以Cell-based方式設計，晶片面積約2.1x2.1 mm2，最大操作頻率在100MHz，平均功耗16mW。

Low power and high performance design issues have played an important role among various portable systems and applications. In embedded processors, the cache design almost occupies half chip area and power consumption. According to Amdahl’s Law, if we could reduce the power consumption of cache, the embedded processor can significantly save more power. The cache miss results in the penalty of thousands of cycles waiting and power consumption due to the increasing external memory accesses. Generally, the set associative cache design could increase the hit ratio, but also induces remarkable power consumption. On the other hand, the phased cache design can largely improve the power consumption which set associative cache wasted, but phase cache requires double access cycles compared with traditional one-access-cycle cache design. In this thesis, we take advantages of the improved pipelined architecture without stalling and low-power phase cache to achieve high-performance and low-power embedded processor design. From experimental results, the proposed architecture could reduce 44% power consumption compared with traditional one-access-cycle cache and eliminate pipeline stalls incurred by phased cache with only 6% gate count overhead. To verify the pipeline architecture, a RISC embedded processor is employed to be the verification platform for the proposed cache controller and pipeline design. The chip fabricated in TSMC 0.18 μm 1P6M CMOS process can operate at 100 MHz, where the whole chip area is 2.1x2.1 mm2. The average power consumption is around 16 mW.