資料位址預測以用來對第一階快取記憶體做電源管理

Abstract

處理器內部的快取記憶體的耗電在整顆處理器的耗電上佔了相當大的比例。隨著製程的進步，靜態耗電的比例會逐漸上升。目前有一個稱之為drowsy cache的技術(每個快取記憶體區塊都有兩種不同的電壓可供選擇)可以有效降低在快取記憶體中的靜態耗電。然而，要喚醒一個處於drowsy狀態的快取記憶體區塊需要消耗額外的時間及能量。而且這個額外的時間會導致整個系統的靜態耗電跟著消耗。本篇論文提出一套預測資料位址的策略，利用該策略來預先打開即將要被存取到的資料快取記憶體。實驗結果顯示，利用我們所提出的這個策略，並與前人的研究做相比，可更進一步地節省資料快取記憶體3%左右的靜態耗電。

On-chip cache is a major chip power consumer. Due to nanoscale technology, the dominant of this power loss will be leakage. The drowsy cache scheme, where one can choose between two different supply voltages in each cache line, is a technique that reduces the leakage energy for cache. Yet, waking up a drowsy line needs extra time and energy, and this extra time would result in total static power consumption. This paper proposes one data address prediction and exploits it to preactivate oncoming cache lines before access requests. Our experimental results indicate that the proposed preactivation policy reduces the power consumption by about 3% (assuming 70nm technology) with respect to previously proposed drowsy cache policies.