應用於無線個人區域網路之低功率互補式金氧半頻率位移鍵/高斯頻率位移鍵收發器設計

Abstract

本篇論文的主旨在於闡述低功率互補式金氧半頻率位移鍵/高斯頻率位移鍵收發器的設計考量及方法。文中首先對常用的收發器架構予以說明，並詳細探討這些架構的優缺點。之後，藉由三個設計實例，深入探討收發器的設計考量及方法。這三個設計實例為：（一）一個低功率可調式互補式金氧半低中頻ㄧ次降頻之單晶片接收器；（二）一個以時間至數位轉換為基礎的高斯頻率位移鍵解調器；（三）一個應用時間至數位轉換數位解調器之低功率2.4-GHz互補式金氧半高斯頻率位移鍵收發器。 第一個設計實例是採用低中頻接收器架構，並搭配頻率位移鍵正交解調器以達到低功率的目標。本設計包含了低功率放大器，混波器，限制放大器，正交解調器，以及頻率合成器等重要電路。此設計是以標準0.25-μm互補式金氧半技術實現在晶片上，並且只佔掉6 mm2的晶片面積。效能方面，此接收器在耗電流33 mA,資料傳輸速率390 kb/s的情況下，可以達到–80 dBm的接收靈敏度。 第二個設計實例提出ㄧ種有別於以往做法的高斯頻率位移鍵解調器。此解調器利用一個時間至數位轉換器將類比帶通訊號轉換成數位基頻訊號。因而，已經發展純熟的數位訊號處理技術可以被利用來增進解調器效能。利用此解調器，接收器便可使用基於限制放大器的架構以達到省電的目的。此解調器是以標準0.18-μm互補式金氧半技術實現在晶片上，並且只佔掉0.26 mm2的晶片面積。該解調器在耗電流2.55 mA,資料傳輸速率1 Mb/s的情況下，輸入訊號雜訊比只需13.9 dB即可達到0.1% 位元錯誤率。 最後一個設計實例是基於使用高斯頻率位移鍵調變方式，提出一包含第二個設計實例所提解調器的低功率收發器。第一個設計實例中所發展的電路技術也被利用到接收器的設計裡。這個收發器是以標準0.18-μm互補式金氧半技術實現在4 mm2的高整合度晶片上。效能上，當接收器操作在耗電流13.3 mA，資料傳輸速率1 Mb/s下，可以達到–89 dBm的接收靈敏度。當發射器操作在耗電流10.7 mA下，可達到0 dBm的發射功率。此外，為符合量產需求，靜電防護設計、製程參數變異、以及溫度、電壓的變化在電路設計過程中均被嚴謹考量。

This thesis presents the design considerations and circuit techniques for implementing low-power CMOS FSK/GFSK transceivers. Commonly used transceiver architectures are introduced first. Advantages and disadvantages of these architectures are analyzed in details. After that, three works are presented to explain the design considerations and circuit techniques. These works include: (1) A Single-Chip Low-Power Tunable CMOS Low-IF Single-Conversion ISM Receiver. (2) A GFSK Demodulator Based on Time-to-Digital Conversion. (3) A Low-Power 2.4-GHz CMOS GFSK Transceiver with a Digital Demodulator Using Time-to-Digital Conversion. The first work employs the low-IF receiver architecture with a FSK quadrature demodulator to achieve the goal of low power consumption. In this work, important building blocks, such as an LNA, a mixer, a limiter and a quadrature demodulator, are included. Fabricated in a standard 0.25-μm CMOS technology, the implemented chip occupies 6-mm2 chip area. With current consumption of 33 mA, the receiver can achieve a sensitivity level of -80 dBm under the condition of 390-kb/s data rate. In the second work, a GFSK demodulator implemented with a novel approach is proposed. In the demodulator, a time-to-digital converter is utilized to converts analog band-pass signals to digital baseband signals. Therefore, the digital signal processing (DSP) techniques can be employed to enhance the demodulation performance. With this demodulator, a limiter-based receiver can be employed to achieve low power consumption. Fabricated in a standard 0.18-μm CMOS technology, the implemented demodulator occupies 0.26-mm2 chip area. With current consumption of 2.55 mA, the demodulator requires minimum input SNR of 13.9 to achieve 0.1% BER under the condition of 1-Mb/s data rate. In the last work, based on the GFSK modulation scheme, a low-power transceiver is proposed, in which the demodulator described in the second work is employed. Circuit techniques developed in the first work are also utilized in the receiver design. Fabricated in a standard 0.18-μm CMOS technology, the implemented transceiver occupies 4-mm2 chip area with a very high level of on-chip integration. In the receiver, with current consumption of 13.3 mA, it can achieve -89-dBm sensitivity level under the condition of 1-Mb/s data rate. In the transmitter, with current consumption of 10.7 mA, it can achieve 0-dBm output power level. Besides, in order to satisfy the requirement of mass production, the ESD design and process, voltage, and temperature (PVT) variations were carefully considered.