應用電容誤差校正技術之CMOS導管式類比數位轉換器

Abstract

在無限通訊系統以及影像或音訊應用中，類比數位轉換器扮演了一個重要的角色。當今，對於低功率、高速及高解析度之類比數位轉換電路有著不可或缺的需求。在許多種類之互補式金氧半類比數位轉器的架構當中，導管式類比數位轉換器幾乎可以同時達到以上所述之三項效能。

在此次研究當中，一個十位元每秒取樣100百萬次操作電壓為1.8伏特的導管式類比數位轉換器，從設計、佈局到製造均使用台積電標準0.18微米互補式金氧半製程來完成，最後並完整地測試晶片。此類比數位轉換器主要包含前端的取樣保持電路、相同8級串接的轉換器，和最後ㄧ級的2位元的快閃式轉換器。所有的類比電路皆以全差動輸入設計，輸入峰對峰1.2V的輸入訊號並且供應電源為1.8伏特。採用每級1.5位元解析度的架構是為了更高之類比數位轉換器之轉換率。同時結合數位錯誤校正技術，可容忍比較器的偏移電壓到某個程度，使比較器不需要前置放大器，進而減少整體的功率消耗。最後，因為製程漂移讓電容發生不匹配而導致的增益錯誤，對於導管式類比數位轉換器來說是無法避免的非線性效應。與過去的傳統架構來比較，此研究應用了”隨機切換電容”的技術來抵抗電容不匹配之錯誤並維持線性度。當類比數位轉換器操作在保持相位時，此方法讓位於一級之內的迴授電容可與取樣電容做隨機的切換，換句話說，這兩種電容角色可以隨機互換。所以在此機制下，每一級發生的電容不匹配錯誤可被平均出來並提昇整體類比數位轉換器之線性度。

此原型設計的類比數位轉換器之模擬表現出在頻率100萬赫茲的輸入弦波訊號下,無寄生動態範圍(SFDR)達到69.43dB，訊號對雜訊加上失真比(SNDR)約為59.15dB且有效位元數將近10位元。最大的微分型非線性誤差為0.55最小位元單位,積分型非線性誤差則是0.7最小位元單位。當我們假設有3%的電容不匹配存在時，實驗結果顯示線性度依然維持住，足以證明此技術之有效性。當輸入80百萬赫茲取樣頻率及100萬赫茲輸入訊號的情形，操作在隨機切換電容模式下，量測到的SNDR為42.73dB、ENOB約為6.81位元;當操作在關閉隨機電容切換模式下，所量測到的SNDR降低為33.57dB、ENOB約為5.28位元。此類比數位轉換器晶片面積約1.87mm2，並在最大取樣頻率100百萬赫茲及1.8伏特電源供應下,共消耗功率88毫瓦。

The analog-to-digital converter (ADC) plays a critical role in wireless communication systems and video/audio applications. Nowadays, the demand for low-power, high-speed, and high-resolution ADC circuit is indispensable. Among many types of CMOS ADC architectures, the Pipelined architecture can almost achieve above three performances at the same time.

In this work, a 10-bit 100MS/s Pipelined A/D converter operated at 1.8V power supply had been designed, laid out, and fabricated with standard TSMC 0.18μm CMOS 1P6M process, and this chip was also measured completely. This ADC mainly consists of one front-end S/H, eight cascaded MDAC stages, and a 2-bit flash converter in the last stage. All analog circuits are fully differential with a 1.2Vpp input signal and 1.8V power supply. A 1.5-bit/stage architecture is adopted for higher conversion rate. Furthermore, incorporating digital error correction technique, which is a successful algorithm of the redundant signed digit (RSD), tolerates comparators offset to some extent and thus no preamplifier is required. Therefore, total power consumption is reduced. Gain error resulted from capacitor-mismatch which is due to process variation, is an inevitable non-linear effect for the Pipelined ADC. As compared with the conventional architecture, this research implements a “random capacitor-swapping” technique against the capacitor-mismatch error and maintains the linearity. This technique makes the feedback capacitor randomly swapped with the sampling capacitor in one stage during the hold cycle of the ADC operation, that is, their roles can randomly interchange. Therefore, the capacitor-mismatch error in each stage can be averaged out, and thus overall Pipelined ADC linearity is improved.

The prototype design of ADC simulation exhibits a peak spurious-free dynamic range (SFDR) of 69.43dB, a signal-to-noise-plus-distortion ratio (SNDR) of 59.15dB and the effective number of bits (ENOB) is about 10-bit with a 1MHz sinusoidal input. The maximum differential non-linearity (DNL) is 0.55 least significant bits (LSB) and the integral non-linearity is 0.7LSB. When we assume that there exists a 3% capacitor mismatch, experimental result shows the linearity still sustain to demonstrate the effectiveness of this technique. At 80MHz sampling rate with 1MHz sinusoidal input, the measured peak SNDR is 42.73dB and ENOB is about 6.81-bit when the capacitor-swapping is on; when the capacitor-swapping is off, the measured SNDR degrades to 33.57dB and ENOB is about 5.28-bit. This A/D chip occupies an area of 1.87mm2 and dissipates 88mW at the maximum sampling rate of 100MHz with 1.8V supply voltage.