數位音訊迴響器之 DSP 晶片設計

Abstract

摘 要 為了增加聽者聆聽的臨場感，產生環場音效以及空間迴響的效果，本篇論文著重於音訊特定空間響應的模擬和訊號處理器硬體實現。所使用的演算法是利用不同的空間有不同脈衝響應，輸入不同空間的特定參數，即可造成空間上的聆聽效果，且適合於雙聲道的撥放系統。此演算法直接實現於所設計的數位訊號處理器，稱為24-bit Low-Cost Processor (LCP24)，並搭配組合語言做最佳化處理。 在這篇論文中，採用了Schroeder 以及Moorer所提出的迴響器為模型並加以改進。這兩種迴響器主要都是採用來四個平行的Comb 濾波器和兩個串聯的All-pass 濾波器來產生直接訊號(Diret Signal)，早期反射(Early reflection)以及指數衰減響應(Fused reverberation)。為了能夠在LCP24上實現一個即時的空間效果音訊處理，修改了此模型，主要是採用一個FIR 濾波器使用以及四個平行的Comb 濾波器和兩個串聯的All-pass 濾波器來產生，直接訊號(Direct Signal)，早期反射(Early refeclation)，指數衰減響應(Fused reverberation) ，最後利用Low-pass 濾波器來增加聆聽的距離感，這樣比全部用IIR filter去實現來的精確。為了達到即時工作的目標，在軟體和硬體的設計上必須以最佳的效率來配合。對於LCP24的實現，在速度和面積上達到Trade off，使用精簡指令集和五級管線式的設計架構。在LCP24內部同時擁有兩個向量處理用的記憶體、四層迴圈、大範圍的記憶體資料暫存區以提供跳躍位址使用，以及擁有24位元精確的浮點運算單元、整數運算單元。乘加指令配合特殊的定址模式，可在一個週期內完成乘加平行的運算。LCP24處理器以Cell-Based方式設計完成，UMC 0.18μm製程之標準元件庫，預估最快可工作於100 MHz，整個晶片面積約為6.5 mm2。

Abstract In order to improve the sense of reality of listening experience, souranding and room effect, this thesis focusing on audio room effect simulation and hardware implementataion of a signal processor is proposed. The algorithm used in this thesis is based on the phenomenon that different audio spaces have different impulse responses. With perticular space parameter,a specific audio room effect is synthetized by signal processor even in multichannel sound system. This algorithm is realized in proposed 24-bit Low-Cost Processor (LCP24) with optimized machine code. In this thesis, the reverberator proposed by Schroeder and Moorer is adopted and modified. These two reverberators include four parallel Comb filters and two all-pass filters in series to generate direct signal, early reflection, and fused reverberation. In order to implement a real-time audio room effect system with LCP24, the reverberator is modified by adding a FIR filter in front of the four parallel filters. A low-pass filter is added to increase the listening space. The modified model is more accurate than original one. For real-time operations, software and hardware are optimized with each other. For LCP24 implementation, the trade off of speed and area is optimized by minimized intructinon set and five-stage pipeline. In LCP24, there are two memories for vector operation, four loops, temporary address memories for returning from subprogram, 24 bits precision floating point operation unit,integer operation unit. It also supports parallel operation of multiplication and summation in a single operation cycle by MAC command and special addressing mode. The chip can be synthesized by COMPASS cell library and realized in UMC 0.18μm 1P6M CMOS technology. The clock rate of the chip is expected to be 100 MHz proved by post-layout simulation and the silicon area required for the core is approximately 6.5 mm2.