軟體無線電之無乘法器取樣率轉換器

Abstract

軟體無線電(Software Radio)必須處理不同種類的通訊標準，這些標準可能使用不同的系統頻率(Master Clock Rate)。為了支援這些標準，比較合理的作法是讓類比轉數位(ADC)和數位轉類比(DAC)轉換器工作在固定的頻率，利用數位的作法改變取樣頻率以支援不同的通訊協定。轉換取樣率的理論是大家熟知的內插器(interpolator)，該裝置可以用來計算取樣信號之間的數值。然而，即使已經有了內插器，內插出的信號可能和正確的信號點，有些微的時序偏差(timing offset)。換句話說，系統仍受限於內插器的解析度。傳統上我們會提高內插器的解析度來處理這個問題，這個方法會需要高階(order)的內插器以及多個乘法器。這篇論文將介紹一套無乘法器的取樣率轉換器。我們會建立取樣時間誤差(timing offset)的數學模型，並用他來解釋一個根本的問題：為什麼需要使用高解析度的內插器。根據這個模型，本論文提出的取樣率轉換器，將可以用較低解析度的內插器，達成較好的效能。最後我們會證明這個架構是簡單而且容易在硬體上實作。跟傳統的作法比起來，只需要些許的修改即可。

Software radio terminals must be able to process many various communication standards. These communication standards are based on different master clock rates. To support these clock rates, a reasonable solution is to clock the ADC and DAC at a fixed master clock rate and perform sample rate conversion (SRC) completely in digital domain. The underlying theory of SRC is well-studied interpolation filter which is used to calculate new samples at arbitrary time in between existing samples. However, even the interpolator is available; available intermediate signal points may not be exactly the desired ones where timing offset may exist. In other words, we are still limited by resolution of the interpolator. To deal the problem, the traditional method is to raise the time-domain resolution to meet the requirement. This way may need high order interpolator which requires multiple general purpose multipliers. In this thesis, a multiplier-free SRC architecture is proposed. We will build the mathematical model for timing jitter and use it to explain the elementary problem that why do we need to employ high resolution interpolator. Based on the model, the proposed SRC architecture could use low resolution interpolator but achieves better performance. Finally, we will show that the proposed SRC architecture is simple and easy to implement. As compared with the traditional approach, only minor modifications are needed.