低功率、低相位雜訊之雙頻帶電壓控制振盪器設計

Abstract

本篇論文的研究焦點著重於降低電壓控制振盪器其功率消耗及相位雜訊的設計。利用電流再利用的架構，可以使電壓控制振盪器在運作時的工作電流只需傳統型電壓控制振盪器運作時的一半而達到低功率消耗的目的。同時，我們也提出在NMOS的基極端外加電阻，此方法可有效降低NMOS熱雜訊進而降低電壓控制振盪器的相位雜訊。根據上述架構及方法，我們完成低功率、低相位雜訊2.5/3.5GHz之雙頻帶電壓控制振盪器。由量測結果(TSMC 0.18-μm 1P6M CMOS 製程)，實作之IC均與模擬結果相近並達到預期之特性。在距離中心頻率10-kHz和1-MHz相位雜訊分別下降7.0dB和4.0dB。此設計的提供電壓為1.3V消耗功率為3.12mW，其工作頻率於2.5GHz和3.5GHz時，相位雜訊在距離中心頻率1 MHz分別為-121dBc/Hz和-117dBc/Hz。

The research described in this thesis focuses on the design of a low power consumption and phase noise LC-VCO. With the current-reused topology, the proposed LC-VCO can operate using only half amount of DC current compared with the conventional topologies to achieve low power consumption. Here, we also propose to add an external resistor at the substrate node of the NMOS transistor, which reduces the substrate thermal noise of the NMOS transistor effectively and the phase noise of the LC-VCO as well. Based on proposed topology and novel method, we implement a low power and low phase noise dual-band LC-VCO, which operates at 2.5/3.5 GHz. The proposed dual-band LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process and the measured results are similar to simulation ones. Therefore, the performances of the proposed LC-VCO achieve anticipation. The result shows that the phase noise reduction is about 7.0 dB and 4.0 dB at 10-kHz and 1-MHz offset frequency, respectively. With only 1.3 V bias voltage and 3.12 mW power consumption, the proposed LC-VCO operates 2.5 GHz and 3.5 GHz with phase noise of -121 dBc/Hz and -117 dBc/Hz, respectively, at 1 MHz offset frequency.